DRV8432 cycle-by-cycle not work for me

Hi Steve,

You have quite a few questions there. I will try to separate and answer them.

Steve Dunn1 said:

pls send to me what the pwma, pwmb waveforrm should look like for cycle-by-cycle mode.

This appears to tie in with the question below about 1% duty cycle on PWMB and 97% on PWMA. I will answer it further down.

Steve Dunn1 said:

i am using pwma 97%, duty cycle and pwmb zero (off) and cycle-by-cycle works perfectly!! why does it work if i am suppose to give pwmb 1% signal to refresh bootstrap capacitor?

The 1% on PWMB is not for the bootstrap. The 1% is to reset the cycle by cycle logic if a current limit is detected. Both PWMA and PWMB must be toggled in the case of a cycle by cycle limit.

Steve Dunn1 said:

my pwm is running at 28kHz and bootstrap capacitor is 100nf / 50v for my dual full bridge and for my parallel full bridge my bootstrap cap is 2.2uf / 50V and i do not place the recommended 5ohm resistor between 12vdc and GVDD-X pins. so why does my parallel full bridge work ok without this 5 ohm resistor? what future problems can i expect because i not have this 5 ohm resistor?

On page 11 of the datasheet, the explanation is that the 5 ohm resistor limits the inrush current into the bootstrap capacitor. On power up, inrush current is larger with a larger value capacitor. This can lead to reliability problems, which is why the 5 ohm resistor is recommended.

Steve Dunn1 said:

If i change the pwmb from zero to 1% duty cycle while the pwma is running at 97% dyty cycle when should the pwmb pulse go high in relation to the pwma pulse? should pwmb pulse go high when the pwma pulse goes low? do they have to be at both same frequency? in syn?

This requires a timing diagram which will be sent later. It will also address the first question.

Steve Dunn1 said:

also my new pcb has the optional Stuff Option capacitors just like the TI evaluation  pcb but they keep exploding when i activate the pwm. why? i thought i needed them for my piston load ( with self monitoring current shut down circuit inside ) but when i remove them i can still work ok. why?

What is the voltage rating of the capacitor you are using and what is PVDD? It sounds like the voltage rating is being exceeded.

Hi Steve,

I noticed that Wilson responded with a timing diagram for cycle by cycle. The post is http://e2e.ti.com/support/applications/motor_drivers/f/38/t/308312.aspx 

Let's use Driving (Fast Decay Synchronous) and Driving (Slow Decay Synchronous) as a starting point for the discussion.

To ensure that cycle by cycle continues to operate, the input pairs PWMA/B or PWMC/D must be toggled each cycle PWM cycle to reset the logic. If the inputs are not toggled and the cycle by cycle limit occurs, the outputs will be disabled and there is no fault indicator.

Please note PWMB is running at the same frequency.

Let us know what questions you have about the two diagrams.

hi rick,

i attach here my el. sch for your review for this discussion.

regarding my exploding capacitors on the outputs they are 47uF / 35V and 2.2uF / 50V.

My gvdd = +12vdc, pvdd = +24vdc

could you send to me the part numbers for these stuff caps on the TI evaluation pcbs?

-Steve

Rick,

regarding the cycle-by-cycle mode. ok i think i get it. is there a TI application note regarding this topic? The idea of 1% pwm on the "off" channel is not mentioned in data sheet is it? I put this 1% pwm in my code and now have the following questions for you. i attach some pics of my dvm and scope.

pic1 shows my normal setup. pwmA running at 97% freq 25kHz. pwmb running at 1% freq 25kHz. no load here.

pic2 pic3:  shows output pwms before power inductors. i have a 3.5ohm resistor loading so load current should be around 7.0amps which i get very nicely from the dual full bridge using the oc adjust resistor of 27kohm (9.7amp). but now i change to 82kohm for 3.4amp limit but i do not see this ti output toggling around the 3.4amp limit. but rather my dvm measures only some 0.243amps. why? and what is this new crazy pwmb signal i am seeing with the double pulse? the first pulse is my 1% but what is the second pulse? is this proof positive that i am successfully in the cycle-by-cycle current limiting mode? yippee.

-Steve

sorry here is my pics in attached zip file.

-Steve

Hi Steve,

could you send to me the part numbers for these stuff caps on the TI evaluation pcbs?

The parts are similar to what you are using 47uF/50V or greater because the EVM handles higher voltages.

Are you trying to set a DC level at the output, like the TEC option (figure 11, page 17) in the datasheet? That is the only time you need those capacitors stuffed.

regarding the cycle-by-cycle mode. ok i think i get it. is there a TI application note regarding this topic? The idea of 1% pwm on the "off" channel is not mentioned in data sheet is it?

There is no application note on this, but the datasheet addresses this issue. It may still be unclear. Please note the second paragraph of page 12.

I am having trouble understanding your comment about getting 7A in pic2, pic3. Are you sure the pictures sent are the ones you intended?

One way to determine the cycle by cycle is working is examining the input vs output. If you have the current limit set low, the output should turn off once the current limit is reached. The input is still commanding the output to be active, but the output has turned off. This should repeat each cycle.

Can you provide a scope capture of inputs vs outputs zoomed in to one cycle?

Thanks.

Hi Rick,

Regarding my pics for the cycle by cycle mode i reposted them in a seperate post in this forum and not in this thread. Could you pls find that post of mine and see if the pics provide you with the information you mention. I simply do not see how those output pwm pulses are suppose to represent the 3.9amps that the resistor is suppose to limit me to. 

-Steve

Hi Steve,

I found the pictures. Link to pictures is: http://e2e.ti.com/support/applications/motor_drivers/f/38/p/373767/1316438.aspx#1316438

A few questions from them.

What are channel 1 and 2 in the pictures?

What are the conditions for TWO.jpg and THREE.jpg? What is the load across the outputs in both images?

There are two potential problems using a DVM to measure current in this system. One is that it is measuring average current. The second is that fast changes in current can create problem with autoranging.

If you have a pure resistive load across 24V, the current will rise and fall quickly. If you have an inductive load, the current will take longer to rise and fall. This should provide a higher average current.

Once you provide the load conditions, I can provide some suggestions to try to measure current.

Rick,

In all pics they are of the output pwmA and pwmB. 

in pic one there is no load and pwmA (channel one) is 97%, pwmB (channel two) is 1%. The output pwmA,B are exactly like my input pwmA,B comng from the FPGA controller I am programming.

In pics 2,3 the load is a 3.5ohm power resistor between the 2 outputs.

In all pics channel 1 is the active pwmA and channel 2 is the inactive pwmB meaning the side i put the 1% pwm signal to per your advice and part is in the half full bridge mode. These are the output pwm signals. My FPGA input pwm signals are exact same as in pic #1.

do you think i am operating in cycle-by-cycle ok? how do i confirm that i am chopping around the 3.9amp per the current limit resistor i put there to create this situation? What is that double pulse on the output pwmB?

-Steve

Hi Steve,

Pic 1:

If your PWM A (channel 1) is 97%, should it be much longer than PWMB (channel 2)?

Why are there two pulses on PWMB?

You appear to be PWM'ing at 25kHz. Based on your description of the inputs, I would expect to see a 38.8us high pulse on PWMA followed by a 400ns pulse on PWMB during the time PWMA was low. The cycle should then repeat.

I see a 3.2us pulse on PWMA and two pulses on PWMB.

Let's make sure Pic 1 is correct prior to moving to current chopping.

Thanks.

Rick,

sorry for all the confusion with my pics and i really appreciate your patience with me and all your help so thanks again. i checked the zip i uploaded and see that i made a mistake in explaining to you what each pic was.

I explain:

PIC #3: this is the output pwmA (ch1) and pwmB (ch2) with no load on them (ie open on each end). I measure on the TI pin itself (i have test points on them) so i measure before and not after the power inductors on the outputs of each pin. it matches exactly to the input pwm A, B that i send from my FPGA controller. both are 25kHz. pwmA is 97% duty cycle so yes your correct pwmA has the much longer high pulse with a short low pulse. pwmB same freq only duty cycle 1% and its low to high edge transition occurs exactly with the low to high edge transition of pwmA. is this not correct to do for pwmB in cycle to cycle mode? is pwmB suppose to have high pulse when pwmA is low? i need clarification on this point because per timing diagrams sent to me that is what it looked like.

PIC #2: this is the output pwmA (ch1) pwmB (ch2) signals after i connect a 3.5ohm power resistor as a load and the DVM in pic shows 0.243amps and not the current limit of 3.9amps that i expected. these pwmA,B look quite different from the pwmA,B that i still send from FPGA controller per pic three above. why? current limit i assume. so can i assume from this that the cycle by cycle mode is operating correctly? and about the DVM measurement ...?

PIC #3: this is a zoom in of pic two for one cycle. and yes my question is what is the double pulse on pwmB channel?

-Steve

Hi Steve,

No worries. Now that we are on the same page, let's go from there.

Pic 3:

Steve Dunn1 said:

pwmB same freq only duty cycle 1% and its low to high edge transition occurs exactly with the low to high edge transition of pwmA. is this not correct to do for pwmB in cycle to cycle mode? is pwmB suppose to have high pulse when pwmA is low?

Ideally, it is preferred to pulse PWMB when PWMA is low. That way you get the full duty cycle.

Steve Dunn1 said:

PIC #2: this is the output pwmA (ch1) pwmB (ch2) signals after i connect a 3.5ohm power resistor as a load and the DVM in pic shows 0.243amps and not the current limit of 3.9amps that i expected. these pwmA,B look quite different from the pwmA,B that i still send from FPGA controller per pic three above. why? current limit i assume. so can i assume from this that the cycle by cycle mode is operating correctly? and about the DVM measurement ...?

The DRV8432 does appear to be regulating current as intended. You can see that after approximately 3us, the output pwmA turns off indicating the current limit was reached. Once pwmA is turned off, the current dies back down to 0.

If you are measuring the current through the resistor with the DVM, it will be the average current per cycle. At best, it will be 3.9 * 4.5us/40us = .44A. In reality the current must build and decay through the inductors. This will reduce the average current measured.

Steve Dunn1 said:

PIC #31: this is a zoom in of pic two for one cycle. and yes my question is what is the double pulse on pwmB channel?

The second pulse is the current through the inductors decaying. Once the outputs are disabled due to cycle by cycle limit, the current must still flow through the inductors. To do this, the current flows through the low side body diode on pwmA and the high side body diode on pwmB. For the current to flow, the pwmA output should be slightly below ground, and the pwmB output should be slightly above PVDD.

The pwm duty cycle should increase as cycle by cycle limit is increased. If you have a current probe, it is a better indicator of the current trip point.

Rick,

ok thanks. now when you say "At best, it will be 3.9 * 4.5us/40us = .44A." pls tell me how you arrived at this 4.5usec value you use? 40usec i understand is my 25kHz frequency or rep rate and 3.9 is max current.

also when you say "Ideally, it is preferred to pulse PWMB when PWMA is low" and i look at the timing diagrams in this thread where there are both the Fast and Slow decay Synchronous and Fast decay Asynchronous you are then saying that i should follow the Fast decay Asynchronous. correct? why you prefer this to the other option of synch? I will program the pwmB signal as you recommend and see what i get as a result later after i return from holiday. 

You see the bigger picture here is that my real world load is not a 3.5ohm resistor but rather a piston that has a worst case scenario startup current of 20amp for duration of 200msec when it is coming out of its absolute down position with a significant weight on it to raise like our heavy metal hospital bed frame. Does TI make a part that could provide me with a max peak current of 20amp for some 200msec? Most of the time i am ok with the DRV8432 because my piston is not in the most extreme case, but ...

-Steve

Hi Steve,

Steve Dunn1 said:

ok thanks. now when you say "At best, it will be 3.9 * 4.5us/40us = .44A." pls tell me how you arrived at this 4.5usec value you use? 40usec i understand is my 25kHz frequency or rep rate and 3.9 is max current.

4.5us assumes that the current is at maximum for both the time the outputs are driven (3.4us - .4us overlap at the beginning of the cycle) + the time the current is recirculating through the body diodes (1.5us).

Steve Dunn1 said:

also when you say "Ideally, it is preferred to pulse PWMB when PWMA is low" and i look at the timing diagrams in this thread where there are both the Fast and Slow decay Synchronous and Fast decay Asynchronous you are then saying that i should follow the Fast decay Asynchronous. correct? why you prefer this to the other option of synch? I will program the pwmB signal as you recommend and see what i get as a result later after i return from holiday. 

I don't mean to imply a preference here. I was simply noting that if you are targeting a specific active duty cycle, I don't think you are acheiving that.

For decay modes, slow decay is preferred in brushed motors.

Steve Dunn1 said:

You see the bigger picture here is that my real world load is not a 3.5ohm resistor but rather a piston that has a worst case scenario startup current of 20amp for duration of 200msec when it is coming out of its absolute down position with a significant weight on it to raise like our heavy metal hospital bed frame. Does TI make a part that could provide me with a max peak current of 20amp for some 200msec? Most of the time i am ok with the DRV8432 because my piston is not in the most extreme case, but ...

The DRV8432 has the highest drive among the current product portfolio. If you desire more current, please take a look at the DRV8711, a predriver that can be paired with external FETs for much higher current.