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DRV3210-Q1 Assertion of the fault flags during power up (45)

Hello,

Please answer following questions from customer.

 

Datasheet has following note on page 13 and 14.

    (2) Assertion of the fault flags may occur during power up.

 

Please answer following question related to this note (2).

Q1: Does this note means that internal fault Flag register may set to “1”?

Q2: Does this note mean that /FALT terminal may go to low?

Q3: Please advise the duration time from fault flag is asserted to deasserted.

 

Best Regards.

  • Toshio-san

    I'm moving this post to this forum for better support.

    Ankur

  • Ushikubo-san,

    Answers in bold

    Q1: Does this note means that internal fault Flag register may set to “1”?

    Yes

    Q2: Does this note mean that /FALT terminal may go to low?

    Yes

    Q3: Please advise the duration time from fault flag is asserted to deasserted.

    To deassert the fault flag you must perform an SPI Read operation on the fault registers to clear


    Regards,

    Will Toth

  • Hello William-san,

    I’m sorry for my delayed response.

    I understand Q1 and Q2.

    Please answer following additional question for Q3.

     

    DRV3210 has FLGLATCH_EN register and it is cleared to “0” while reset, so I believe FAULT flag returns to “0” even if FAULT is asserted during power up.

    If my understanding is correct, please advise duration time from fault flag is asserted to de-asserted.

     

    Best Regards.

  • Hello William-san,

    Please answer above my question of Q3.

    Best Regards.

  • Ushikubo-san,

    Sorry for the confusion, your understanding is correct, the FLGLATCH_EN register will be 0 at reset, thus the flags will not latch and all fault flags will return to "0" once the fault is no longer present.

    So to answer your original question:

    Q3: Please advise the duration time from fault flag is asserted to deasserted.

    It depends on when each specific fault clears and the timing for that fault

  • Hello William-san,

    Thank you for your answer.

    I need time information how long does it take to de-assert fault flag.

    Please refer attached file and advice duration of fault assertion time of attached file (min/max).

    NO.45_1.pptx

    Best Regards.

  • Ushikubo-san,

    To be clear, you want to know the time from when /RES goes high until all fault flags have cleared?

    Thanks,

    Will Toth

  • Hello William-san,

    Yes.

    Best Regards.
  • Hello William-san,

    Please answer for my question.

    Best Regards.
  • Ushikubo-san,

    I need to set this up on my bench, I will get back to you with results tomorrow.

    Regards,
    Will Toth
  • Hello William-san,

     

    Thank you for your reply.

    Please let me known results.

     

    Best Regards.

  • Ushikubo-san,

     

    The /RES line and the /Fault lines are independent of each other, and depend on different faults. If we look at the logic for the /FAULT signal (datasheet pg 12):

     

    And if we compare it to the logic for the /RES signal (datasheet pg. 6 & 7)

     

     

    From here you can see that the /FAULT pin does not have any dependency on VCCUV. Conversely, /RES does not have any dependency on several other signals including VBUV. This means that it is possible for the /RES signal to go high, while the /FAULT pin stays low. Here are three scope shots that show three different scenarios.

    For the below scope captures:

    Blue: VCC

    Yellow: /RES

    Green: /FAULT

    Purple: VB

    Scenario 1:

    VB ramps quickly to 5V, VBUV and all other faults are cleared and /FAULT goes high. VCCUV (and other signals not plotted) is cleared and after tON /RES comes up.

     

    Scenario 2:

    VB is set to ~4.3V, but on this device is lower than the threshold for VBUV, so /FAULT stays low. VCC comes up to its proper value so VCCUV is cleared and after tON /RES comes up. /FAULT stays low.

     

    Scenario 3:

    VB is set to ~4.3V, slightly above the threshold for VBUV, so /FAULT goes high, however VCC comes up before VBUV is cleared, so VCCUV is cleared and after tON /RES comes up. In this case /RES comes up before /FAULT. This is highly dependant on how fast VBUV is cleared based on the ramp rate. You can see that near the target VB ramps slowly, but VCC regulates to above VCCUV quickly.

    So for your question

    Q3: Please advise the duration time from fault flag is asserted to deasserted. To be clear, you want to know the time from when /RES goes high until all fault flags have cleared?

    It depends on your system. During power up, each flag  will clear when the associated fault is cleared. In the diagram you provided (NO.45_1), the fault flags may all be cleared already (t = 0), the fault flags may not be cleared but is highly dependent on your system (t > 0), or the fault flags may never clear as in Scenario 2 above (t=inf).

    Regards,

    Will Toth