When reading STAT1 register, the non-sticky error bits are cleared automatically during/after read. In my code, I read STAT1 after the fault pin is asserted to determine the cause of the error. While purposely causing an over-current fault on one of the FETs, I see that the fault bit in the STAT1 is asserted, but none of the FETHx_OC, or FETLx_OC bits are asserted. By changing how I perform the read I can actually see which FETxx_OC bit set.
I believe my problem is that the actual register read operation is actually occuring later than I originally expected, and causing the FETxx_OC bits to be cleared before I shift out the read value. However, I want to make sure of this.
Any read of any DRV8301 register requires that first a read command be shifted in with a 16bit SPI transfer, and then the result be shifted out with another 16bit SPI transfer. So the operations for a single register read looks like something like this:
- Assert chip select
- Shift out 16bit read command, (ignore data that is shifted out)
- De-assert chip select
- Assert chip select
- Shift in 16bit result (shift out some "dummy" command, in my case a read of STAT1)
- De-assert chip select
I has assumed that register was read soon after step 3, and moved over to output shift register. However, after some testing I'm get the impression that the register read actually occurs at just after 4 when the chip-select is asserted. This also means that what ever command that was happen to be present in the command register is executed during step 1. In my case a STAT1 read command is often present in the command register before step 1, which causes the FETxx_OC bits to be cleared, before the code actually reads them in step5.
I can fix my code using a different "dummy" command for step 5. This way the STAT1 error bits are not clear when I shift in a new command.
The other option is that I always leave a STAT1 command in the SPI register after every operation. This way reading STAT1 only takes 1 SPI transfer.
Could someone verify that SPI read command is actually executed when next chip select occurs (step4), instead of when command is received (step3)? The datasheet doesn't really specify this.
