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DRV8805 Dead time at 2-Phase exection

Other Parts Discussed in Thread: DRV8805

Hi

My customer is using DRV8805.
He drives uniporor stepping motor by 2-Phase exection.
Is there dead time between OUT1_ON->OUT1_OFF and OUT3_OFF->OUT3_ON?

Best regards
Shimizu

  • Shimizu,

    There must be dead-time between on-off trasnstions of OUT1 &3 and Out2 &4 for full step 2-phase excitation step. I could not find the figure in data-sheet, so I will contact the desginer and some-one motor application team will answer the query.

    Best Regards

    Milan-Motor Application Team

     

  • Hi Shimizu,

    I'm a little confused why there will be needed for a deadtime in between the all lowsides driver. Anyway for the internal index logic transfering from one state to another, there will be very small delay from the analog circuits. But not like normal deadtime between High/Los sides, this time interval in DRV8805 should not be sensitive to the application.

    Best regards,
  • Hi Wilson

    Thank you for your support.
    Actually, My customer has issue.
    This question was done to look for its cause.

    Issue is "under shoot" at being to "ON" integrated FET.
    Please see attached file.

    I think that this event is not cause of FET ON.
    When _X became simultaneously "ON" with X in uniporor motor, is there a possibility which becomes such event?

    Best regards
    Shimizu

    issue.pptx

  • Hi Shimizu,

    I'm not seeing this on EVM bench. Could you give the DRV8805 schematic and motor spec?
    Also could you give more explain on the plot in the slides?

    Best regards,
  • Hi Wilson

    Thank you for your support
    I confirm detail of this isuue to customer.
    Please wait.

    I'd like to know the detail about deadtime.
    You wrote "very small delay" at previous post.

    How long is time of deadtime?
    Does Deadtime show "time" between the gate driver sink to OUT1_FET OFF and gate driver source to OUT3_FET ON?

    Thanks
    Shimizu
  • Hi Wilson

    Thank you for your support.

    I'm sorry.
    My customer made a mistake.
    Waveform which sent previous post is TD62064AFG's waveform.
    There is Zener diode between VM and COMMON pin.

    My customer say that "If there is Zener diode between VM and VCLAMP pin at DRV8805 and not deadtime, DRV8805 outputs about -0.7V from OUT pin at FET_ON".
    I don't know this mean.
    Does your check of EVM open JP3 on EVM?
    Could you advice me about customer's comment?

    Sorry an abstract question.  

    Tnanks
    Shimizu
  • Hi Shimizu,

    Thank you! Also I just got reply from designer that there is no deadtime between the logic states in DRV8805.
    JP3 on EVM could be open or closed, and I tested both with no abnormal. It is recommended with the Zener diodes to fast decay the current in high speed motor driving application or fast ON/OFF valve controls.

    For the -0.7v customer seeing, one possible reason is the unpolar motor has the self induction in each of the magnet core shared two coils. That will be seen but with no affecting to the motor running.

    Best regards,
  • Hi Wilson

    Thank you for your advice.

    I knew the following post.
    You teached me. Thanks.
    e2e.ti.com/.../1366932

    In this situation, it is impossible to be voltage level in abusolute maximum rating.
    Is this no problem?

    Best regards
    Shimizu
  • Hi Shimizu,

    This effect only pulls down the output voltage.

    But the clamping TVS/Zener will lift up the VM and outputs voltage to the VM+0.7+Vclamping level. Please make sure this sum is < maximum rating and leave some margin there. Also using the worse case of the Vclamping voltage.

    Best regards,