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[DRV8312] Switching problem with high current pulse

Other Parts Discussed in Thread: DRV8312

Dear TI's experts,

I'm using DRV8312 to do sensorless BLDC algorithm without TI's library. I met a problem with the switching schematic:

When a phase is in Hi-Z stage, at the first times working, its voltage was near 9.5V. Then I do switching none complementary and this Hi-Z phase is changed to current returning switch, it is connected to PGND immediately. This cause very high current (I-total) and make the COMP output toggle to high. This effect to TZ module that I use to do current protection. Thus the current fault is always active in stage switching transition. 

Could you please share me if I do something wrong? or is there any way to avoid this situation? 

Regards,

Fitz

  • Hi Fitz,

    Could you give a drawing of your question for us to better understand you problem?
    Also the COMP minitor should have some filter/blanking structure to remove the switching noise caused by parasitic inductance mainly.

    Best regards,
  • Hi Wilson,
    To quickly discuss, I would describe the problem as:

    Example: When switching line is A->B, phase C is floating. At the beginning, Va, Vb, Vc = 9.5V (all floating). So If I set RESET_A, RESET_B high and RESET_C low to enable phase A, B, still floating phase C on DRV8312 to do PWM. Right after that, there is a high pulse of I-total which is set as input for COMP1. This make COM1P event occurs and clear all PWM signal to do fault protection.

    Regards,
    Fitz
  • Hi Fitz,

    Let me assuming this way. Firstly, switch from A->B, floating C. Non-complementary. So in PWM OFF, the current is retaining through AB low side (Slow decay). Then the next commutation, Ex. A floating, C->B PWM. The retaining(recirculation) current of AB will take both AB fast decay and AB Slow decay based on the ON/OFF of B low side. So there will be sometime before the AB current decay to zero, the I_total will be the I_drive_CB + I_slowdecay_AB. This is the possible current makes your system tripped. Complementary PWM should reduce this I_total.

    Usually how long time will be the COMP OC output? if it is ~mS level, it should be the one discussed above. If it is ~uS level, it should be the parasitic inductance bouncing discussed on previous post. We can mask this period in the current feedback loop.

    Best regards,
  • Dear Wilson,

    Yes, the current pulse is not far 1us. It's the parasitic inductance bouncing. I will try to increase the filter for COMP module then inform you the result later.

    Thank you for your support.

    Regards,
    Fitz