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DRV8832

Other Parts Discussed in Thread: DRV8832, DRV8830

Would you tell me about these questions?

1) How long time does it take to become "FAULTn = Low" after OCP is worked?

We suppose a process below;

1. Output current of over 1.3A continue about 275ms.
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2. DRV8832 detect OCP
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(I would like to ask you the necessary time between 2. and 3.)
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3. FAULTn become to Low.

2) After FAULTn becomes low, how long time should I set IN1 and IN2 low to enable DRV8832?

  I understand there are 2 methods with VCC and IN1/IN2 to enable DRV8832.

Best regards,
Y.Hirata

  • Hi Hirata-san,

    Are you referring to OCP (Section 7.3.5) or Current Limit (Section 7.3.6.1)?

    If OCP, FAULTn is typically less than 1us. Power cycle is required to recover from OCP.

    If current limit, FAULTn is approximately 275ms. We will have to check the IN1/IN2 low time to re-enable.

  • Duncan-san,

    Thank you for your reply.
    I am sorry there is a place that knows wrong.
    I would like to discuss OCP.

    I wont to clear DRV8832 from OCP with IN1 and IN2.
    How long time should I set IN1 and IN2 low to enable DRV8832?

    Best regards,
    Y. Hirata
  • Hi Hirata-san,

    The DRV8832 requires a power cycle to clear the OCP. The time of the power cycle will depend on the bulk cap.

    The DRV8830 with an I2C interface can be clear the OCP using the CLEAR bit.
  • Hi Rick-san,

    Allow me to cut in.
    At page 7 'Bridge Control' on datasheet, it is mentioned
    'When both input are low ........... Current limit fault condition is also cleared.'

    First IN1 is high and IN2 is low. OCP function operates and latch off.
    The customer clear this condition with IN1, IN2 are low.
    The customer wants to know the minimum low time to clear the condition.
    Could you tell me the minimum low time?

    Regards,
    Naoki Aoyama
  • Hi Aoyama-san,

    We will investigate and reply soon. I think there has been a mis-understanding.

    There is overcurrent (OCP) described in section 7.3.6.1 of the most recent datasheet and Current Limit described in section 7.3.5.
    The OCP is a one time event >1.3 for typically 2us. The current limit requires typically 275ms to trigger.

    Can you confirm the customer is asking about the current limit which requires ~275ms?
  • Hi Aoyama-san,

    Sorry for the delay.

    Both the OCP (output short circuit to GND/VCC/other output resulting in outputs disabled) and the current limit (Vrsense >200mV for ~275ms) can be cleared by placing the device in sleep mode.

    To do so, place the device in sleep (IN1=IN2=Logic low) for a minimum of 10us.
  • Hi Rick-san,

    Thank you for your reply.
    I needed the value '10us'.
    Thank you very much.

    Naoki Aoyama