DRV8872(Q1) in sleep state

Hi Someno-san,

We do not have this data available.

Any impedance from OUTx to VM and OUTx to PGND is included in the total Ivmsleep.

Can you explain why the customer wants this data?

Hi Rick-san,

Thanks for your reply.

The reason why customer requests this data is;

This part has been specified as OUTx with Hi-Z in sleep mode. So,When customer put this part in sleep mode with a pull-up resister at OUTx, OUTx shows about VM/2 voltage, not VM voltage.  So, customer asks why it shows VM/2 and the impedance from OUTx to VM and OUTx to GND to determine OUTx voltage.

I knows the specification of  IVMSELLP on datasheet. But it should include IC's bias current with total impedaance from OUTx-GND and OUTx-VM,too.  And also, the impedance from OUTx-GND and OUTx-VM in sleep mode is not same (because MOSFET at highside and low side is different) and the impedance ratio should set OUTx voltage.

Can you confirm the designer or anyone their impedanse?  Rough impedanse(or estimation) is OK.

Best regards,

Hidekazu Someno

Hi Someno-san,

What is the VM voltage? Also, what is the value of the pullup resistor from OUTx to VM?

There is a path through a zener and diode to a pulldown resistor on the high side gate. If more than approximately 7V is present on the OUTx pin when the device is in sleep mode, current can flow.

The impedance depends on what is placed on the output when in sleep. If unloaded, the impedance is many MOhms with leakages in the tens of nA.

Rick-san,

I just checked OUTx voltage by using FLUKE tester under the following conditions on DRB8872EVM.

Conditions: VM=12V, IN1=IN2=GND, OUTx=open(Only Rpullup or Rpulldown)

1. Pullup

     1M --> OUTx=around 6.2-6.3v,  100ohms --> around 10.3v

2. Pulldown

     100k --> OUTx=0.0v,  1M --> around 50m-100mV

Please check them.

Best regards,

Hidekazu Someno

Best regards,

Hidekazu Someno

Hi Someno-san,

The pullup value makes sense, but the pulldown value does not.

We will check. This may take a few days.

Hi, Rick-san,

Did you have anything with your checking about that?

Bes regards,
Hidekazu Someno

Hi Someno-san,

Yes, I do. The pulldown value makes sense according to the design team.

Sorry for the delay, and thank you for reminding me.

Rick-san,

Finally, How much is internal inpedanse of OUTx-VM and OUTx-GND in sleep mode?
That was the original question from customer. Please tell me the impedance value in sleep mode(OUTx=HiZ).

Best regards,
Hidekazu Someno

Hi Someno-san,

I don't think I can give you one value.

When there is no voltage on the outputs, the impedance varies from 2MOhms up. There is some small leakage until approximately 6V, when the leakage exceeds 1uA. The device VM is 12V and the measurements were taken at 25C.

Above 6V, the impedance begins to decrease from 2MOhms @6.2V to 600 Ohms @ 11V. This was measured with VM=12V.

Below 6V, the impedance varies from 200MOhms at 2V to 4.5MOhms at 6V.

Rick-san,

Thanks.

About the circuit decreasing impedance at VOUTx>6v,
In the previous mail, I found your explanation that "There is a path through a zener and diode to a pulldown resistor on the high side gate."
- Is This the the circuit?
- What is the purpose of the internal circuit to decease impedance, protection of high side FET's against reverse VGS?

Best regards,
Hidekazu Someno

Hi Someno-san,

Yes, this is the circuit.

And yes, the purpose of the circuit is to protect high side FET against reverse VGS.