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DRV8860 about Fault Register Reset issue and enable pin isssue

Mickey Zhang
Genius 12080 points
Other Parts Discussed in Thread: DRV8860

Hi Team,

The customer has two questions for DRV8860.

1.  For Fault Register Reset question:

If the Data register is written 0 and the nFAULT pin is floating, is the OL(Open Load Detection) flag bit 1 or 0? At this time, execute the Fault Register Reset command and then  read the fault register, is the OL(Open Load Detection) flag bit 1 or 0?
 
2. For the enable pin question:
The enable pin is needed to pull down the low logic when the registers can be read and written in the datasheet.

But the customer does a test. The test result shows a high level or a low level  for the enable pin cannot affect the registers read / write operation.

That is  the registers can be read and written correctly when the enable pin is  a high level or a low level.
How to set the enable pin? If the enable pin is needed to pull down the low logic, will the output state for DRV8860 be changed?

Best Wishes,
Mickey Zhang
Asia Customer Support Center
Texas Instruments



  • 0
    TI__Guru** 114905 points

    Hi Mickey,

    1.  For Fault Register Reset question:

    If the Data register is written 0 and the nFAULT pin is floating, is the OL(Open Load Detection) flag bit 1 or 0? At this time, execute the Fault Register Reset command and then  read the fault register, is the OL(Open Load Detection) flag bit 1 or 0?


    What do you mean "the nFAULT pin is floating"?

     

    2. For the enable pin question:

    The enable pin is needed to pull down the low logic when the registers can be read and written in the datasheet.

    Are you referring to the pin description of the ENABLE pin:

    Logic high to enable outputs, logic low to disable outputs. Internal logic and control input registers can be read and written to when ENABLE is logic low. Internal pulldown.

    The description may be confusing. It means that the the control registers can be read and written independent of the ENABLE state.

  • 0 in reply to Rick Duncan
    TI__Genius 12080 points

    Hi Rick，
    Thanks for your support.
    1. For Fault Register Reset question:
    Sorry, the customer does not describe in detail to me.
    If the Data register is written 0 and the output pins are floating, is the OL(Open Load Detection) flag bit 1 or 0?

    At this time, execute the Fault Register Reset command and then read the fault register, is the OL(Open Load Detection) flag bit 1 or 0?

    The customer would like to know after the Fault Register Reset command is executed, is the fault register  always cleared or  temporarily

    cleared?

    2. For the enable pin question:
    You mean when the enable pin is a high logic or a low logic, the control registers can be read and written normally, right?

  • 0 in reply to Mickey Zhang
    TI__Guru** 114905 points

    Hi Mickey,

    1. For Fault Register Reset question:
    Sorry, the customer does not describe in detail to me.
    If the Data register is written 0 and the output pins are floating, is the OL(Open Load Detection) flag bit 1 or 0?

    At this time, execute the Fault Register Reset command and then read the fault register, is the OL(Open Load Detection) flag bit 1 or 0?

    The customer would like to know after the Fault Register Reset command is executed, is the fault register  always cleared or  temporarily

    cleared?



    The fault should be temporarily cleared. If the fault remains after the open load fault is still present after the fault reset, nFAULT will re-assert. I have not been able to confirm this because the GUI used does not have this feature.

    2. For the enable pin question:
    You mean when the enable pin is a high logic or a low logic, the control registers can be read and written normally, right?


    Correct, registers can be read when enable pin is a high logic or low logic.



  • 0 in reply to Rick Duncan
    TI__Genius 12080 points
    Hi Rick,

    Thank you for your help.
  • 0 in reply to Rick Duncan
    TI__Genius 12080 points
    Update:

    Hi Rick,

    For Fault Register Reset question:
    The customer would like to know how long the fault register is temporarily cleared.

    After the fault register is temporarily cleared, is the the result of the register quickly refreshed by the actual result?
  • 0 in reply to Mickey Zhang
    TI__Guru** 114905 points
    Hi Mickey,

    I measured the time to be 17us from the LATCH signal rising to the fault reasserting. This is consistent with the Tol parameter in the datasheet.