DRV8301
Hi,
Apart from the overcurrent circuit of the DRV8301,
the overcurrent detection circuit of the motor is provided externally.
When PVDD is suddenly changed from 20V to 24V, the external overcurrent detection circuit detects overcurrent,
It is designed with a circuit that sets the EN_GATE of the DRV8301 to Low.
(The objective is to stop the operation of DRV 8301 because an overcurrent has been detected)
A Low pulse is output to nFAULT immediately after EN_GATE is set to Low.
24V is applied to PVDD.
Let me check the specification of DRV8301.
Question: Is nFAULT function valid even when EN_GATE is set to Low?
The data sheet(page20) has the following comments.
"It will then wait for 10us before completely shutting down the rest of the blocks."
From the time EN_GATE goes low until 10us, can the nFAULT circuit be considered valid?
best regards
cafain
