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DRV8308: SPI SCLK Timing

Andy Bartfay
Prodigy 90 points
Part Number: DRV8308

The DRV8308 datasheet specifies a minimum SPI clock (SCLK) cycle time of 62 nS (~16 MHz).  The evaluation board runs the clock at 1 MHz.  On our custom hardware, I've found that transfers do not work properly for frequencies above ~2 MHz.  This is well below the specified limit.  Is this a known deficiency?

Thanks.

  • 0
    TI__Guru** 114905 points
    Hi Andy,

    Is the problem with writes or reads? If reads, what value pullup resistor do you have? The pullup resistor can affect the read of the data.

    If writes, please zoom in on the transaction and look for noise on the SCLK that could be interpreted as an extra clock.
  • 0 in reply to Rick Duncan
    Prodigy 90 points

    Rick,

    Thanks for your response.
    When running with a faster clock (~10 MHz) read data looks like a right-shifted version of what was written.  E.g writing 0x00FF returns 0x003F, writing 0x0FFF returns 0x003FF.
    SCLK, SCS and SDATAI all look clean.  SCLK has no spurious edges.  The pullup on SDATO is ~10k and the rising edges of SDATAO are fairly fast.  I'll try a lower value pullup.

    Andy