Other Parts Discussed in Thread: DRV8711, MSP432WARE,
I am at a loss on this. All of the appropriate pins are configured according to the IC's datasheet and the pinout on the BoosterPack. My code is attached. It starts with a single write to the CTRL register, followed by repeated reads in an endless loop. I have tried this with other registers; all have ended with the same results. What other debugging steps can I try?
/* * ------------------------------------------- * MSP432 DriverLib - v3_21_00_05 * ------------------------------------------- * * --COPYRIGHT--,BSD,BSD * Copyright (c) 2016, Texas Instruments Incorporated * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * --/COPYRIGHT--*/ /****************************************************************************** * MSP432 Empty Project * * Description: An empty project that uses DriverLib * * MSP432P401 * ------------------ * /|\| | * | | | * --|RST | * | | * | | * | | * | | * | | * Author: *******************************************************************************/ /* DriverLib Includes */ #include "driverlib.h" /* Standard Includes */ #include <stdint.h> #include <stdbool.h> // My includes #include "BoosterPackInterface.h" static uint16_t packet = 0; static uint8_t txByte = 0; //void spi_init() //{ // SpiaRegs.SPICCR.bit.SPISWRESET = 0; // reset during configuration // // // set configuration control register fields // SpiaRegs.SPICCR.bit.SPICHAR = 0xF; // 16-bit transactions // SpiaRegs.SPICCR.bit.CLKPOLARITY = 0; // data output on rising edge, input on falling // SpiaRegs.SPICCR.bit.SPILBK = 0; // disable loopback // // // set operation control register fields // SpiaRegs.SPICTL.bit.CLK_PHASE = 1; // no phase delay for data // SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1; // master mode on // SpiaRegs.SPICTL.bit.TALK = 1; // enable data output from this master device // SpiaRegs.SPICTL.bit.SPIINTENA = 0; // disable SPI interrupt // // // set baud rate via maximum clock division in baud rate register // SpiaRegs.SPIBRR =0x007F; // set rate of transmission to slowest possible // // // exit reset state // SpiaRegs.SPICCR.bit.SPISWRESET = 1; // done with configuration; clear reset // // // keep CCS from messing with the transmission // SpiaRegs.SPIPRI.bit.FREE = 1; // Set so breakpoints don't disturb xmission // SpiaRegs.SPIPRI.bit.STEINV = 1; // active high CS // SpiaRegs.SPIPRI.bit.TRIWIRE = 0; // 4-wire SPI //} /* SPI Master Configuration Parameter */ const eUSCI_SPI_MasterConfig spiMasterConfig = { EUSCI_B_SPI_CLOCKSOURCE_SMCLK, // SMCLK Clock Source 3000000, // SMCLK = DCO = 3MHZ 50000, // SPICLK = 500khz EUSCI_B_SPI_MSB_FIRST, // MSB First EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT, // other phase option //EUSCI_B_SPI_PHASE_DATA_CHANGED_ONFIRST_CAPTURED_ON_NEXT, // Phase default EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW, // Low polarity EUSCI_B_SPI_3PIN // 3Wire SPI Mode }; int main(void) { /* Halting WDT */ WDT_A_holdTimer(); /* Selecting P1.5 P1.6 and P1.7 in SPI mode */ GPIO_setAsPeripheralModuleFunctionInputPin(GPIO_PORT_P1, GPIO_PIN5 | GPIO_PIN6 | GPIO_PIN7, GPIO_PRIMARY_MODULE_FUNCTION); // configure CS pin GPIO_setAsOutputPin(GPIO_PORT_P3, GPIO_PIN6); //////////////////////////////////////////////////////////////////////////////////////////// // Configure GPIO //////////////////////////////////////////////////////////////////////////////////////////// // Port 6.0 is analog input from pot GPIO_setAsInputPin(GPIO_PORT_P6, GPIO_PIN0); // Ports 3.2, 3.3, 4.1 are inputs (NC) GPIO_setAsInputPin(GPIO_PORT_P3, GPIO_PIN2); GPIO_setAsInputPin(GPIO_PORT_P3, GPIO_PIN3); GPIO_setAsInputPin(GPIO_PORT_P4, GPIO_PIN1); // Port 4.3 is nSLEEP output (active low) GPIO_setAsOutputPin(GPIO_PORT_P4, GPIO_PIN3); // Port 4.6 is RESET output (active high) GPIO_setAsOutputPin(GPIO_PORT_P4, GPIO_PIN6); // Port 6.5 is STEP output GPIO_setAsOutputPin(GPIO_PORT_P6, GPIO_PIN5); // Port 6.4 is DIR output GPIO_setAsOutputPin(GPIO_PORT_P6, GPIO_PIN4); // Port 2.5 is nSTALL input GPIO_setAsInputPin(GPIO_PORT_P2, GPIO_PIN5); // Port 3.0 is nFAULT input GPIO_setAsInputPin(GPIO_PORT_P3, GPIO_PIN0); // Port 5.7 is an input (NC) GPIO_setAsInputPin(GPIO_PORT_P5, GPIO_PIN7); // Port 5.0 is B1 output GPIO_setAsOutputPin(GPIO_PORT_P5, GPIO_PIN0); // Port 5.2 is B2 output GPIO_setAsOutputPin(GPIO_PORT_P5, GPIO_PIN2); ///////////////////////////////////////////////////////////////////////////////////////////// // Initialize GPIO ///////////////////////////////////////////////////////////////////////////////////////////// // drive nSLEEP high (not in sleep mode) GPIO_setOutputHighOnPin(GPIO_PORT_P4, GPIO_PIN3); // drive RESET low (not in reset) GPIO_setOutputLowOnPin(GPIO_PORT_P4, GPIO_PIN6); // set STEP output low GPIO_setOutputLowOnPin(GPIO_PORT_P6, GPIO_PIN5); // set DIR output high GPIO_setOutputHighOnPin(GPIO_PORT_P6, GPIO_PIN4); // set B1 output low GPIO_setOutputLowOnPin(GPIO_PORT_P5, GPIO_PIN0); // set B2 output low GPIO_setOutputLowOnPin(GPIO_PORT_P5, GPIO_PIN2); /* Configuring SPI in 3wire master mode */ SPI_initMaster(EUSCI_B0_BASE, &spiMasterConfig); /* Enable SPI module */ SPI_enableModule(EUSCI_B0_BASE); // write to CTRL reg first packet = WRITE | CTRL_ADDR | DEADTIME_850 | SENSE_GAIN_40 | MODE_EIGHTH | ENABLE_MOTOR; while(1) { GPIO_setOutputLowOnPin(GPIO_PORT_P3, GPIO_PIN6); // reset CS pin _delay_cycles(10000); /* Polling to see if the TX buffer is ready */ while (!(SPI_getInterruptStatus(EUSCI_B0_BASE,EUSCI_B_SPI_TRANSMIT_INTERRUPT))); GPIO_setOutputHighOnPin(GPIO_PORT_P3, GPIO_PIN6); // assert CS pin /* Transmitting data to slave */ txByte = packet >> 8; SPI_transmitData(EUSCI_B0_BASE, txByte); // transmit packet[15:8] while (!(SPI_getInterruptStatus(EUSCI_B0_BASE,EUSCI_B_SPI_TRANSMIT_INTERRUPT))); txByte = packet; SPI_transmitData(EUSCI_B0_BASE, txByte); // transmit packet[7:0] _delay_cycles(850); // hold CS high packet = READ | CTRL_ADDR; // from now on, read from the CTRL register } }