DRV8305: Mean of VPVDD-SH_X and power supply voltage

Part Number: DRV8305

Dear all,

Could you teach us how to use VPVDD-SH_X value?

And could you teach us whether our usage of power supply is correct?

We think to separate supply voltage to DRV8305 from N-ch MOS with three cases.

case 1. supply 24V or 12V to DRV8305, 10V to N-ch MOS

case 2. supply 12V to DRV8305, 24V to N-ch MOS

case 3. supply 24V to DRV8305, 24V to N-ch MOS (but power supply to MOS is turn ON/OFF by MCU)

If our usage are wrong, could you teach us the reason?

Best regards,

  • Hi Yamamoto-san,

    Thank you for pointing this out. The recommended VPVDD-SH_X should be 45V. This will be corrected in a future datasheet update.

    There are problems with separating PVDD and VDRAIN as described.

    Case 1a: supply 24V to DRV8305, 10V to N-ch MOS
    Violates Abs max PVDD - VDRAIN, plus high side VGS is ~24V (could damage FETs)

    Case 1b: supply 12V to DRV8305, 10V to N-ch MOS
    This should operate correctly. High side VGS is ~12V instead of 10V

    Case 2: supply 12V to DRV8305, 24V to N-ch MOS
    Violates Abs max PVDD - VDRAIN, plus high side VGS is -2V (does not enable high side FETs)

    case 3. supply 24V to DRV8305, 24V to N-ch MOS (but power supply to MOS is turn ON/OFF by MCU)
    Violates Abs max PVDD - VDRAIN when MOS power is off. This could be corrected with a few extra components to keep PVDD-VDRAIN within the spec.

    Rick Duncan
    Motor Applications Team

  • In reply to Rick Duncan:

    Hi Duncan-san,

    Thank you for your answers.
    Could I make sure about Case 1a and 1b?

    I have understood about Abs max PVDD - VDRAIN, but I have not understood about later text.
    Will high side VGS be ~34V in case 1a, and ~22V in case 1b because of charge pump(PVDD+10V)?
    Therefore, with Abs max of 'Internal phase clamp pin voltage difference', did you answer 1a has problem and 1b is OK?

    Is my idea correct?

    Best regards,
  • In reply to Takao Yamamoto:

    Hi Yamamoto-san,

    Will high side VGS be ~34V in case 1a, and ~22V in case 1b because of charge pump(PVDD+10V)?
    Therefore, with Abs max of 'Internal phase clamp pin voltage difference', did you answer 1a has problem and 1b is OK?

    Correct. Case 1a has problems. Case 1b is OK.

    Case 1a: The high side gate voltage will be ~34V. The gate to source voltage will be ~24V. Many FETs are not rated for this. This also violates the Abs max of 'Internal phase clamp pin voltage difference'

    Case 1b: The high side gate voltage will be ~22V. The gate to source voltage will be ~12V.

    Rick Duncan
    Motor Applications Team