Other Parts Discussed in Thread: TINA-TI,
Tool/software: TINA-TI or Spice Models
Hi
I am simulating the PMP10783 design on TINA same as schematic of PMP10783 but why output voltage is not coming? VDD voltage is increasing to UVLO level and again going down and turns off IC.1715.PMP10783_startup.TSC What can be reason for that? why
what can be a problem? is it a design problem or TINA tool problem?PMP10783_startup.TSC