PMP9720: PMP9720 issue

Hi,

Any updates? Thank you!

Tom

Hi Brian,

Spec. Vin=30-55v Vout=12.8V fs=200kHz

I’ve changed Ron=91k R104=100k. Others are almost the same. Thank you!

Tom

Hi Brian,

I'm here to update my circuit data.

fs=200kHz
T1: 6:4:4 (pri : aux : sec)
C14: 0.2uF
R3: 0 ohm
Q5 is opened
Removed T2, R5 and added a current sense resistor(0.05 ohm) which is series with Q6.
R19=91k
R22=100k
L1=10uH
C9=990uF
The Coss of my Q6 and Q7 is 1700pF.
Other components are almost the same.

I've used a 54ohm resistor to replace L5, otherwise, my aux. voltage will drop while load on.

My SR MOSFET cannot open correctly in light load. I think the reason why is that my circuit is in DCM mode, and it is resonant dramatically.
The DCM resonant phenomenon cause my VSEC1 and VSEC2 are not a pretty square waveform. So that, two of my gate drive will open at the same time.
Is there any method to solve this problem like reduce the resonant phenomenon at DCM mode. Please give us some suggestion.

Thank you!

TOM

Hi Tom,

I see that you have changed the transformer.  What is the magnetizing inductance of your transformer?

The synchronous rectifier drive on this circuit forces CCM operation at light loads, so the phenomenon you are describing must be due to something else.  Does it work better with load on it?  Can you send some scope images of the waveforms?

thanks,

Brian

Hi Brian,

My magnetizing inductance is 50uH.

Waveforms are shown as attached.

Ch1: VSEC1, Ch2:VSEC2, CH3: IL, Condition: very light load and disconnect gate driver with SR MOSFET

Ch1: VSEC1 to GND, Ch2:OUTH of U4 to GND, CH3: VSEC2 to GND, CH4:OUTH of U1 to GND Condition: very light load and disconnect gate driver with SR MOSFET

Thanks A LOT!

TOM

Hi Brian,

In addition, I cannot show you the waveforms which SR gate drivers are connected with SR MOSFETs. Once, they are connected, my SR MOSFETs would be damaged. Thanks!

TOM

Hi Tom,

I think you need a longer delay time for the SR FETs that you have chosen.  Try the following procedure:

1. Replace the SR driver circuit and increase R14 to 100k.

2. See if it runs at no load.  It should be forced CCM, so there should not be a DCM ring.

3. Observe the Vds waveform of Q7 at min Vin and max Vin.  You need to look for hardswitching and excessive body diode conduction time.

4. Adjust R14 to avoid hardswitching and minimize body diode conduction time.  

I can help you with steps 3 and 4.  

What is the part number of your SR FETs?

thanks,

Brian

PT_UCC2897A SR FET damage issue-2.pptx6886.PT_UCC2897A SR FET damage issue-2.pptx

Hi Tom,

I apologize for my slow response.  I was on vacation yesterday. 

The switching speed of the NTMFS5C628NLT1G FET is too slow:

Rise time: 150ns

Turn-off delay: 28ns

Fall time: 70ns

To get similar performance to the original PMP9720 design, you should use SR FETs with similar switching characteristics to the CSD18532Q5B FETs.

thanks,

Brian

Hi Brian,

I have one more question.

The Bias is not stable at light load(Vin=30V, turn ration:6:4:4 Aux. winding parameters are the same as yours) in my circuit.

I have also tried remove L and used a small resistor(56 ohm) to replace it can solve light load unstable condition. However, The Vcc will exceed the IC operation voltage in higher Vcc(55V) or in heavy load.

Is there any solution for this?

Thanks a lot!

Best,

Tom

Hi Tom,

Is the supply now working in forced CCM?  If you are still operating in DCM, the L-C filter for the bias will not work.  Here is an alternative way to generate the bias instead of using the L-C filter:

Modified Bias.pdf

thanks,
Brian

Hi Tom,

Good to hear that it works!   For latching SCP, it is best for you to use the secondary side current sense as the trigger for your SCR.  The primary current sense signal will be limited to 500mV by the pulse-by-pulse current limit.

thanks,

Brian

Hi Tom,

Here is a simple latch circuit that you can use.  In your case, you will need to use a current limit comparator trip the latch rather than the SS cap. 

regards,

Brian