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Original question:

ADC for seismic data acquisition system

ADC for seismic data acquisition system: Processor to handle the amount of data from multiples ADCs

Sara Souza
Expert 1450 points
Other Parts Discussed in Thread: ADS1282, CC1352R, ADS1287D, ADS1283, ADS1287

Hi, I followed all the discussion here:  https://e2e.ti.com/support/applications/ti_designs/f/1009/t/565858 and I have a similar question.

In my case I choosed the ADS1282 also for my seismic application. But after  suggested that each chip should be responsible for only one input I realized I  need 6 ADS1282 chips for my project. I also need to send data via wireless communication. For this I choosed the CC1352R microcontroller. But I don't know if only CC1352R will care of it all.

  • 0
    TI__Mastermind 22935 points
    Hey Sara,

    I see the ADC you want to use has a SPI output. There is not enough SPI pins on the CC1352 to support all that directly but if you time multiplex the ADC signals you can support all of them on one device. Obviously that comes at the cost of throughput but at least you don't need additional hardware. It all depends on your system requirements but short answer, yes you could. You just need to make sure there's timing agreements across the devices.

    Regards,
    JP
  • 0 in reply to Jesu
    Expert 1450 points

    I get it... As I told here in the question description I saw in the post which originates this one that is "it's not practical to multiplex between these channels due to the long settling time of the digital filter." And that was the reason I  told here I need 6 ADS1282 (one per input).

    But if the only problem in multiplexing the channels is the settling time, maybe I should evaluate 2 scenarios:

    1. Using multiple ADS1282 in a single SPI interface; 

    2. Using AD1282 with it's inputs being multiplexed. 

    And see if the  SPI multiplexing time is shorter or bigger than the settling time from  ADS1282 multiplexing.

    Do you think this is the calculation I should do or maybe there's is other question beyond settling time I should consider?

    Thanks,

    best regards,

    Sara 

  • 0 in reply to Sara Souza
    TI__Mastermind 22935 points
    Hey Sara,

    Not sure what they mean by not practical. It all depends on what the requirements are.

    Say you just need to take a sample once every 10 seconds (random number) which is long enough to not have to worry about any hardware related timing (assumption). Then it wouldn't be practical to add a hardware multiplexer in your design because you can get the job done without it.

    I recommend you think about the high level requirements of your system (i.e. timing, throughput, power...), then look through the documentation of the devices to see if it meet the requirements of your system.

    Regards,
    JP
  • 0 in reply to Jesu
    Expert 1450 points

    Hi Jesu,

    I see.. I already have the requirements: one sample of all inputs at each 1ms, that means at a 1 kHz frequency. Each input sample is 24 bits resolution. If I use 3 ADCs each one multiplexing 2 inputs I should set each ADC to work at at least 2kHz (I mean at least because there is the time of changing between one input to another).

    I also have to take in account the time for buffering it all at the SPI interface: in order to have all inputs in one single mili second the spi interface should also multiplex between the 3 ADCs, at a frequency of 6kHz (because it should read the 3 first outputs from the 3 ADCs and it should back before 0.5 ms has been elapsed to read the another 3 multiplexed inputs from the same 3 ADCs).
    Without take in account the auxiliary bits from the communication, the SPI interface should have a bit rate of 6*24 bits / ms = 144000 bps. (SPI clock of 144kHz without modulation).

    By the way, I just took a look right now into the ADS1282 datasheet, I am not familiar to ADCs details, but as I am trying to understand better about the settling time, at the table "Electrical Characteristics " (page 4, ADS1282 datasheet), it says that given some conditions (one of them fDATA = 1Ksmps), the settling time is 62/fDATA what obviously gives a period bigger than 1/fDATA. Although I am still not familiar to settling time concept at all, I was thinking how the settling time could be bigger than the sample rate since the sample rate ensures me the rate that data is made available.

    best regards,

    Sara Monteiro

  • 0 in reply to Sara Souza
    TI__Mastermind 44550 points

    Hi Sara,

    The ADS1282's data length is 31-bits, so you will have to clock at least four bytes on the SPI on read the data. If you use the read data "by command" mode, then each data read operation must also be proceeded with a one byte command. In total, you may have to clock 40-bits, but to allow for some margin lets just say you'll be clocking out 50-bits. The maximum SCLK frequency for the ADS1282 is 2.048 MHz (assuming a 4,096 MHz fCLK), so it will be a minimum of about 25 us (or 50 bits / 2.048 Mbps) to read the data from one ADC. Knowing that, you should be able to read out the data from six different ADCs within the 1ms period (for the 1 kSPS data rate) on a single SPI bus.

    However, keep in mind, this doesn't take into account any other delays you might encounter in your system due to post-processing of the data (i.e. any math operations you may want to perform on the data), or the amount of time it make take to output this data through another interface. So you will need to consider if you have any other delays in your system which might present a bottleneck.

    NOTE: I don't know of any advantage of running the SCLK at a slower frequency. Therefore, I would recommend running it as fast as you can to allow yourself the most timing margin.

    Sara Souza said:
    By the way, I just took a look right now into the ADS1282 datasheet, I am not familiar to ADCs details, but as I am trying to understand better about the settling time, at the table "Electrical Characteristics " (page 4, ADS1282 datasheet), it says that given some conditions (one of them fDATA = 1Ksmps), the settling time is 62/fDATA what obviously gives a period bigger than 1/fDATA. Although I am still not familiar to settling time concept at all, I was thinking how the settling time could be bigger than the sample rate since the sample rate ensures me the rate that data is made available.

    I can comment on this as well...

    Think of the digital filter as having 62 taps and waiting at least 62 conversions for each of these taps to get filled with data (without this data, the digital filter's calculation is "unsettled"). This is sort what the digital filter is doing, and the first "settled" result will only be provided after 62 conversion periods. However, after this initial settling time, you will get new conversions results output at the normal data rate interval (and the filter's output result will only be operating on the last 62 conversion results).

    It is due to this long filter settling time, that I wouldn't recommend trying to achieve a high data throughput when MUX'ing with the ADS1282. Each time you switch the MUX channel or the PGA gain, the digital filter will reset (all the filter taps will default to zero) and you'll have to wait for at least 62 conversion periods for the filter to provide the next settled output.

    I hope that helps!

    Best regards,
    Chris

  • 0 in reply to Christopher Hall
    Expert 1450 points
    Perfect Christopher,
    Thanks for clarifying!

    I agree to you in running the SCLK at a faster frequency in order to have the rest of the time to get the data and store it. As I am going to use CC1352R I just figured out that it has a module called "Sensor Controller" with serial interfaces and dedicated CPU what can optimize this work. Now I just need to study it more.

    P.S 1: I could not understand exactly what "taps" mean. (maybe because I could not find a suitable translation for my language, or maybe because I still do not know ADC concepts details), but I think I got the main idea: that "settling time" is a kind of set-up time for the ADC to calibrate its digital filter, that it takes 62 periods of the sampling frequency and it happens when initializing the channel and while multiplexing it, right?

    P.S 2: I think you meant 4.096 MHz instead of 4,096 MHz (Only saying because dots and commas may cause some confusion to others).

    best regards,

    Sara Monteiro
  • 0 in reply to Christopher Hall
    Expert 1450 points

    Hi Christopher Hall,

    after our discussion I started to design the architecture of my application, then I just realized that in spite of ADS1282 be compatible with SPI interface, it doesn't have a CS (chip select) pin, instead of this, it has a DRDY pin (Data Ready) that provides a signal to inform that the data is available. The problem is that this makes it impossible to choose which chip I want to select to hear the ADC result. I would need a single SPI dedicated to each ADC, what is by far impracticable.

    Then, I was wondering if I could use the ADS1287D at the place of ADS1282, since it is also for seismic and energy exploration, it fits exactly for my application (24 bits, 1 Ksmps ) and the best: I would need the half quantity since it has 2 simultaneous channels (not multiplexed) and also has CS pins to select the channels I want to speak to.

    What do you think?

    Do you think I must have another concerns?

    Is there some problem I should know in working with the maximum sample rate (1Ksmps) using the both simultaneous channels? ( because I need to have data in this exactly rate, not less)

    thanks once more,

    best regards,

    Sara

  • 0 in reply to Sara Souza
    TI__Mastermind 44550 points

    Hi Sara,

    You are correct... there is not a /CS pin on the ADS1282 and this does make it difficult to interface to multiple ADCs. This issue can be worked around by gating off the SCLK signal through a MUX (as shown here); however, I realize this is still not ideal.

    Another option would be to replace the ADS1282 with the ADS1283. This is a similar device with comparable performance and lowered power consumption. The ADS1283 also added a /CS pin.

    The ADS1287D is a good option for space-contained designs; however, do note that both the SNR and power consumption of the ADS1287 and ADS1287D are lowered, so the performance is not quite at the level of the ADS1282 or ADS1283. The ADS1287D only runs up to 1 kSPS, and you would need to clock out both channels of data within this conversion period; however, I don't see any issue with doing so, especially if you are using the /DRDY interrupts to quickly service the read data operation after a conversion period completes. I also believe the reference voltage and input range scaling is a bit different on the ADS1287/87D devices, so do take care when selecting the correct reference voltage.

    Let me know if you have any additional questions about these devices!

  • 0 in reply to Christopher Hall
    Expert 1450 points

    Hi Christopher,

    Yes, I also thought about using a switch circuit (in this case a MUX), but I also don't think it's an elegant solution, besides adding more components for my design, increasing the complexity, timing for switching, etc.

    ADS1283 sounds good, I'll consider.

    But enjoying this opportunity, I can see that ADS1287, for example, has a SNR of 116 dB while ADS1283 has a SNR of  130 dB. And then, ADS1283 would be more suitable because the SNR is greater, right?

    Using the formula SNR=6.02*N+1.76dB to calculate the maximum possible SNR for N number of bits, I can see that the maximum SNR for ADS1287 would be : 146.24 dB [(6.02×24)+1.76] and for ADS1283: 188.38 dB [(6.02×24)+1.76]. And then the difference for the ADS1287 is 30.24 dB and the difference for the ADS1283 is 58.34 dB, then I thought if I should take in account the smaller differences  or what really matters is only the given SNR (116 and 130) in this case.

    Thanks,

    best regards,

    Sara


  • 0 in reply to Christopher Hall
    Expert 1450 points
    Ah,
    what you meant with "space-contained designs"?
  • 0 in reply to Sara Souza
    TI__Mastermind 44550 points
    Hi Sara,

    The SNR equation you're using assumes that you're using an ideal ADC that only exhibits quantization noise. For lower-resolution ADCs, it is possible to achieve SNR's close to their ideal limits, but once you start moving into 16-bit ADCs and higher, you'll notice that thermal noise starts to show up and the '6.02*N' equation no longer describes the actual performance of the ADC.

    The reason the ADS1287's SNR is a lower than the ADS1283 is because it is optimized for lower power consumption, which is generally a direct design trade-off with performance.

    The ADS1287D has 2 ADC's (not just two channels) in a 5x5-mm package, whereas the ADS1287 is a single ADC in a 5x4-mm package. Therefore, you can fit more ADC's into a smaller PCB area if that is one of your design constraints.

    I hope that helps provide some clarity.

    Best regards,
    Chris