Linux/DRA722: J6E boot up stuck in SPL

Part Number: DRA722

Tool/software: Linux

Hi all,

We have custom daughter board + custom DRA722 CPU module board with uboot 2014.07 in glsdk 7.03.00.00.3 , but some our CPU modules which filter out by our MP line are bad.

Because those CPU modules can not boot up successfully , the boot log only print 4 lines.

U-Boot SPL 2014.07 (Apr 26 2017 - 16:16:36)
DRA722-GP ES1.0
DPLL locking failed for 4a0052a8
### ERROR ### Please RESET the board ###

So I tracked source code and found the problem is occurred on this function,

	if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
			   (void *)dpll_regs->cm_idlest_dpll, LDELAY)) {
		printf("DPLL locking failed for 0x%x\n",
		       dpll_regs->cm_clkmode_dpll);
		hang();
	}

Could you give us some direction to debug it ? ( it should be h/w issue , but we want to know which part is NG )

I'm looking forward to your reply, thank you.

Best Regards,

Bowe Ren

  • Hi Ren,

    Ren Bowei
    DPLL locking failed for 4a0052a8

    4a0052a8 is the physical address of the CM_CLKMODE_DPLL_GMAC register. The problem with your board is that DPLL_GMAC can not be locked.

    Ren Bowei

    So I tracked source code and found the problem is occurred on this function,

    	if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
    			   (void *)dpll_regs->cm_idlest_dpll, LDELAY)) {
    		printf("DPLL locking failed for 0x%x\n",
    		       dpll_regs->cm_clkmode_dpll);
    		hang();
    	}

    You provide code from u-boot/arch/arm/cpu/armv7/am33xx/clock.c, but it seems to me this error message comes from u-boot/arch/arm/cpu/armv7/omap-common/clocks-common.c

    static inline void wait_for_lock(u32 const base)
    {
        struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;

        if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
            &dpll_regs->cm_idlest_dpll, LDELAY)) {
            printf("DPLL locking failed for %x\n", base);
            hang();
        }
    }

    Can you check again if this message is generated from within clock.c or clocks-common.c?

    Ren Bowei
    Could you give us some direction to debug it ? ( it should be h/w issue , but we want to know which part is NG )

    Check the source/reference clock of the DPLL_GMAC, compare it with the working boards. The source/reference clock is GMAC_DPLL_CLK, derived from SYS_CLK1 (OSC0).

    Check also vdda_core_gmac analog power supply, it should be 1.8V with max noise (peak-peak) 50 mVppmax

    Regards,
    Pavel

    Note:  If this answer solves your question please click the "Verify Answer" button.


  • In reply to Pavel Botev:

    You can also check OSC0 parameters, make sure it covers the requirements described in DRA72x DM, section 6.1.2.1 OSC0 External Crystal

    Note:  If this answer solves your question please click the "Verify Answer" button.


  • In reply to Pavel Botev:

    Dear Pavel,

    I have checked voltage of the vdda_core_gmac and clock of the GMAC_DPLL_CLK. They are all correct.

    Best Regards,
    Bowei Ren
  • In reply to Ren Bowei:

    Ren,

    Have you check OSC0 parameters? Make sure it covers the requirements described in DRA72x DM, section 6.1.2.1 OSC0 External Crystal.

    You can also use CCStudio and run GEL file to see if DPLL_GMAC will be locked there. See the below pointers for more info:

    www.ti.com/.../sprac17a.pdf

    ccsv6/ccs_base/emulation/gel/DRA72x/DRA72x_prcm_config.gel -> dpll_gmac_config(), DRA72x_PRCM_Clock_GetConfig(), DRA72x_PRCM_Clock_Config_API()

    Regards,
    Pavel

    Note:  If this answer solves your question please click the "Verify Answer" button.


  • In reply to Pavel Botev:

    Hi Pavel,

    I run DRA72x_prcm_config.gel by CCStudio, but I cannot find dpll_gmac_config() and DRA72x_PRCM_Clock_Config_API().
    The result of DRA72x_PRCM_Clock_GetConfig() as below:
    =================================================================
    CortexA15_0: GEL Output: --->>> Reading DPLL configurations...<<<---
    CortexA15_0: GEL Output: Frequency values are as per M/N/etc...
    CortexA15_0: GEL Output: MPU:
    CortexA15_0: GEL Output: DPLL in LOCK_MODE mode
    CortexA15_0: GEL Output: DPLL CLKOUT_M2 speed is 1041 MHz
    CortexA15_0: GEL Output: DPLL CLKOUT_M2 is ACTIVE

    CortexA15_0: GEL Output: CORE:
    CortexA15_0: GEL Output: DPLL in LOCK_MODE mode
    CortexA15_0: GEL Output: DPLL CLKOUT_M2 speed is 554 MHz
    CortexA15_0: GEL Output: DPLL CLKOUT_M2 is GATED

    CortexA15_0: GEL Output: ABE:
    CortexA15_0: GEL Output: DPLL in IDLE_BYPASS_LOW_POWER mode
    CortexA15_0: GEL Output: DPLL CLKOUT_M2 speed is 0 MHz
    CortexA15_0: GEL Output: DPLL CLKOUT_M2 is GATED

    CortexA15_0: GEL Output: IVA:
    CortexA15_0: GEL Output: DPLL in IDLE_BYPASS_LOW_POWER mode
    CortexA15_0: GEL Output: DPLL CLKOUT_M2 speed is 0 MHz
    CortexA15_0: GEL Output: DPLL CLKOUT_M2 is GATED

    CortexA15_0: GEL Output: DDR:
    CortexA15_0: GEL Output: DPLL in LOCK_MODE mode
    CortexA15_0: GEL Output: DPLL CLKOUT_M2 speed is 693 MHz
    CortexA15_0: GEL Output: DPLL CLKOUT_M2 is ACTIVE

    CortexA15_0: GEL Output: DSP:
    CortexA15_0: GEL Output: DPLL in IDLE_BYPASS_LOW_POWER mode
    CortexA15_0: GEL Output: DPLL CLKOUT_M2 speed is 0 MHz
    CortexA15_0: GEL Output: DPLL CLKOUT_M2 is GATED

    CortexA15_0: GEL Output: GMAC:
    CortexA15_0: GEL Output: DPLL in LOCK_MODE mode
    CortexA15_0: GEL Output: DPLL CLKOUT_M2 speed is 260 MHz
    CortexA15_0: GEL Output: DPLL CLKOUT_M2 is ACTIVE

    CortexA15_0: GEL Output: GPU:
    CortexA15_0: GEL Output: DPLL in IDLE_BYPASS_LOW_POWER mode
    CortexA15_0: GEL Output: DPLL CLKOUT_M2 speed is 0 MHz
    CortexA15_0: GEL Output: DPLL CLKOUT_M2 is GATED

    CortexA15_0: GEL Output: PER:
    CortexA15_0: GEL Output: DPLL in LOCK_MODE mode
    CortexA15_0: GEL Output: DPLL CLKOUT_M2 speed is 100 MHz
    CortexA15_0: GEL Output: DPLL CLKOUT_M2 is GATED

    CortexA15_0: GEL Output: PCIE:
    CortexA15_0: GEL Output: DPLL in IDLE_BYPASS_LOW_POWER mode
    CortexA15_0: GEL Output: DPLL CLKOUT_M2 speed is 0 MHz
    CortexA15_0: GEL Output: DPLL CLKOUT_M2 is GATED

    CortexA15_0: GEL Output: Clock inputs to different modules:
    CortexA15_0: GEL Output: DPLL in IDLE_BYPASS_LOW_POWER mode
    CortexA15_0: GEL Output: DPLL CLKOUT_M2 speed is 0 MHz
    CortexA15_0: GEL Output: DPLL CLKOUT_M2 is GATED

    CortexA15_0: GEL Output: IPU1 functional clock is CLKOUTX2_M2 from ABE DPLL.
    CortexA15_0: GEL Output: IPU1 CPU speed is 0 MHz

    CortexA15_0: GEL Output: IPU2 functional clock is from CORE DPLL (CLKOUTX2_H22).
    CortexA15_0: GEL Output: IPU2 CPU speed is 0 MHz

    CortexA15_0: GEL Output: GPU CORE clock is from CORE DPLL (CLKOUTX2_H14).
    CortexA15_0: GEL Output: GPU CORE clock speed is 0 MHz
    CortexA15_0: GEL Output: GPU HYD clock is from CORE DPLL (CLKOUTX2_H14).
    CortexA15_0: GEL Output: GPU HYD clock speed is 0 MHz
    CortexA15_0: GEL Output: --->>> Reading DPLL configurations...done<<<---
    =================================================================
    For these information, have any suspect point?

    Best Regards,
    Bowei
  • In reply to Ren Bowei:

    Bowei,

    Ren Bowei
    but I cannot find dpll_gmac_config() and DRA72x_PRCM_Clock_Config_API()

    These are invoked from:

    DRA72x_PRCM_Clock_Config_OPPNOM_DRA72x_GENERIC()

    DRA72x_PRCM_Clock_Config_OPPNOM_DRA722()

    Please try with these two functions. Run on both working and non-working boards and compare the results.

    Ren Bowei
    The result of DRA72x_PRCM_Clock_GetConfig() as below:

    Ren Bowei
    CortexA15_0: GEL Output: GMAC:
    CortexA15_0: GEL Output: DPLL in LOCK_MODE mode
    CortexA15_0: GEL Output: DPLL CLKOUT_M2 speed is 260 MHz
    CortexA15_0: GEL Output: DPLL CLKOUT_M2 is ACTIVE

    Do you run this function only on non-working board? If yes, please run also on working board and compare the results.

    Looks like DPLL_GMAC can be locked from withing GEL file. So you might have another issue for your non-booting board.

    Can you try with removing Ethernet/CPSW support from your u-boot code base to check where your boot flow will go? You can do that with removing the below line in u-boot/include/configs/dra7xx_evm.h

    - #define CONFIG_DRIVER_TI_CPSW

    Then the DPLL_GMAC will be not initialized in u-boot/arch/arm/cpu/armv7/omap-common/clocks-common.c

    static void setup_dplls(void)
    {

    ....

    #ifdef CONFIG_DRIVER_TI_CPSW
        params = get_gmac_dpll_params(*dplls_data);
        do_setup_dpll((*prcm)->cm_clkmode_dpll_gmac, params,
                  DPLL_LOCK, "gmac");
    #endif
    }


    You can also do the same (remove CPSW support from u-boot) for your working board and compare the result (boot log).

     

    Regards,
    Pavel

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  • In reply to Pavel Botev:

    Hi Pavel,

    Following the steps what you suggestion.
    I removed Ethernet/CPSW support and boot flow can go. But still stucking another place (original place will not be stuck).

    According to this phenomenon, it looks like DPLL_GMAC has some problems, is this correct?

    Best Regards,
    Bowei
  • In reply to Ren Bowei:

    Bowei,

    Yes, most probably the problem is in the clock that supply DPLL_GMAC. Can you enable again Ethernet/CPSW support and just remove/comment the below line. Will you have the same result?

    u-boot/arch/arm/cpu/armv7/omap-common/clocks-common.c

    static void setup_dplls(void)
    {

    ....

    #ifdef CONFIG_DRIVER_TI_CPSW
    params = get_gmac_dpll_params(*dplls_data);
    //do_setup_dpll((*prcm)->cm_clkmode_dpll_gmac, params, DPLL_LOCK, "gmac"); --> remove this line
    #endif
    }


    Regards,
    Pavel

    Note:  If this answer solves your question please click the "Verify Answer" button.


  • In reply to Pavel Botev:

    Pavel,

    I removed the line what you suggestion. The boot flow can go and boot up successfully.
    But I have a question, why the mac still workable in the Linux after I remove this line.

    BTW, many thanks for your support.

    Best Regards,
    Bowei Ren