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We are using X5777BXGABC processor in one of our design.Where I'm not able to access DDR3L chips(1GB) which has connected to the EMIF2 controller.
I tried connecting JTAG with reduced clock but not able to access any of the DDR registers.
One thing i could observe by probing is that CKE of EMIF2 is not toggling.Its idle as high(Vtt).
Can any one help me further debugging this issue.
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In reply to Yordan Kamenov:
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In reply to Dobrin Dobrinov:
In reply to Anand Ram Karanth:
I also thought about HW issue but first wanted to confirm everything is OK from SW side.
High level of CKE is normal. According to DDR3 JEDEC spec (JESD79-3F) CKE is low only during Self Refresh and Power Down commands. It must be high during reads and writes. Here is an excerpt:
Could you please send the LISA_MAP_i register settings just to verify everything is OK?
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