We are using X5777BXGABC processor in one of our design.Where I'm not able to access DDR3L chips(1GB) which has connected to the EMIF2 controller.
I tried connecting JTAG with reduced clock but not able to access any of the DDR registers.
One thing i could observe by probing is that CKE of EMIF2 is not toggling.Its idle as high(Vtt).
Can any one help me further debugging this issue.
In reply to Yordan Kamenov:
Please click the Verify Answer button on this post if it answers your question.
Please make sure you read the forum guidelines first.
In reply to Dobrin Dobrinov:
In reply to Anand Ram Karanth:
I also thought about HW issue but first wanted to confirm everything is OK from SW side.
High level of CKE is normal. According to DDR3 JEDEC spec (JESD79-3F) CKE is low only during Self Refresh and Power Down commands. It must be high during reads and writes. Here is an excerpt:
Could you please send the LISA_MAP_i register settings just to verify everything is OK?
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with respect to these materials. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.