DRA744: HOW TO Display 2880x960 resolution by using extended display features and 2 VOUT

Hi All,

Looking to weston is looks like is possible to have an extended mode (omapdrm exteded mode).

Can we have confirmation from the DSS expert this is a solution we can use in production. I mean can be sure that there are no risk of "dirty areas" or vsync issues?

We will have a needle on the center to the screen that need to be painted to 60 fps.

BR,

Fabio

Hi Venkat,

Drive two displays using the same PLL as clock source and one divisor for each of the two displays. according to the  follow picture should be possible.

Possible software configurations (implemented in drivers/gpu/drm/omapdrm/dss/dpi.c):

• LCD1 on PLL1_1 and LCD2 on PLL1_3
• LCD2 on PLL2_3 and LCD3 on PLL2_1
• LCD1 on PLL1_1 and LCD3 on PLL1_3

Unfortunatelly,  using two LCDs that shares the same PLL does not work with current SDK (3.01.00.03):

My Team tried to make this modification but  when one LCD is enabled, the other dies.

Is this a configuration never tested in TI, Can you maybe share some more details?

Hi Venkat,

Thank you very much, we Enabled use of same PLL for 2 Vout, then also applied the Hack enabling M4 and M6 divider.

In this way we got the 2 display working!!

Unfortunately  there is some phase displacement between the 2 display clocks. This phase displacement is also not constant . It fluctuate at every reboot.

Is there some settings we can use to be sure the 2 Vout will have a deterministic phase displacement?

Attached the wave form of the clock in 2 different measure ( Please consider only the Delta phase, Amplitude and wave form can be due the probes used).

Measure 1:

Measure 2:

Hi Venkat,

We apply another hack, in order to enable the Vout ad the same time (2 instruction in sequence) ( by the way not using atomic activation).

Please see the Vsync, the 2 Vout are still not in sync, see the attached picture.

We can still try do reduce this time between the 2 Vout Vsync, but i belive will be really difficult to keep it in sync, What do you think? Can you suggest something else to try?

Looking to the Datasheet we also verify that a resolultion 2800x960@60fps is teorically supported from the HDMI output (187MHz).

Do you think this could be a backup solution for us?

We are working for a very important customer case and we would like to walking around all the details and all the possibility we may have to solve this big issue. Can we organize a conference Call with our FAE (Carlo Colombo) and decide next steps?

BR,

Fabio

Hi Venkat,

Looking to the datasheet: DSS clock, Figure 11-4. Display Subsystem Clock Tree e Table 11-86. DISPC Clocks and Resets

We believe is  possible to bypass the PLL VIDEO Clock and  generate the Display clock directly from the  DSS_CLK,

Can we set  the display 1 end display 2 the DSS_GFCLK and then adjust the H12 divider. With this instruction can we have the vsync and clock in sync between the 2 displays?