Linux/DRA722: dra722 vout2 cannot enable lcd2 output

samgyung zhang

Part Number: DRA722
Other Parts Discussed in Thread: DRA72

Tool/software: Linux

hi,I met a problem.My project required to support two lcd displays,vout1 is enable to support lcd1 output on default,so i try to enable the vout2 to support lcd2 alone at first,but i did'nt work.I have upload some files in the attatchment.The pinmux configuration is in the dts.txt,the IO_delay configutation is in the mux_data.txt,I also run the dss_dumclocks.sh to get some message,I am so confuse that while read from DSS_CTRL ,that i find some trace like that "DPI1 output : HDMI",as you can get the detail messages from the dss_dumclocks.txt in the attachment.what's more,after i run the dmesg,i find some message like that "omap_crtc_flush() timeout" 、"registered panic notifier" and etc.I am totally new guy to TI DSS system,can you give me some help?Thank you very much!

TO TI.rar

over 7 years ago

0 Yordan Kamenov over 7 years ago

TI__Mastermind 42515 points

Hi Samgyung,

can you clarify which version of SDK/kernel you use and also is it an EVM or custom board?

Regards,
Yordan

0 samgyung zhang over 7 years ago in reply to Yordan Kamenov

Expert 1060 points

hi,Yordan,

It is base on sdk7.04.00.03,kernel 3.14,it is not evm board,but base on dra722,thank you!

0 Yordan Kamenov over 7 years ago in reply to samgyung zhang

TI__Mastermind 42515 points

Hi Samgyung,

this SDK is quite old, there is SDK ver 3.02 with much newer kernel 4.4:
processors.wiki.ti.com/.../Category:Processor_SDK_Linux_Automotive

Is there any reason you use such old SDK?

Regards,
Yordan

0 samgyung zhang over 7 years ago in reply to Yordan Kamenov

Expert 1060 points

HI Yordan Kamenov ,
Moving kernel3.14 to kernel4.4 is not suitable for our current project,it will take some unexpected risk for us,we will use the newer sdk in the futrue,but not now.From the attatchment that you can give me some directions?Thank you very much!

0 Yordan Kamenov over 7 years ago in reply to samgyung zhang

TI__Mastermind 42515 points

Hi Samgyung,

I have forwarded your question to an DSS expert.

Regards,
Yordan

0 Stanislav Stilyanov over 7 years ago in reply to samgyung zhang

TI__Genius 15120 points

Hi Samgyung,

There exist several threads to date regarding multiple VOUTs. Please search for them in Automotive Forums.
Most probably it is a clocking problem.
Besides the threads I'm referring to, you can also download and install the interactive Clock Tree Tool. It will help you to understand the DSS clocking.

0 samgyung zhang over 7 years ago in reply to Stanislav Stilyanov

Expert 1060 points

hi,Stanislav Stilyanov :
thanks for your advise,I found some patch below for kernel 3.14 to support lcd2 output,and it work!And you can suggest the others who meet the similar problems to have a try!
review.omapzoom.org/37626
review.omapzoom.org/37627

Another question, Is that LCD1 output is corresponed to DPLL_VIDEO1 while on the other hand that LCD2 output is corresponed to DPLL_VIDEO2?My project is based on dra722,as far as i know,dra722 only have DPLL_VIDEO1,do not have DPLL_VIDEO2.Is that mean that dra722 cannot support dual display at the same time?From the TRM,i quietly not understand the DPLL_VIDEO1 because the descriptions is little.Thanks !

0 Stanislav Stilyanov over 7 years ago in reply to samgyung zhang

TI__Genius 15120 points

Hi,

Good to hear you solved your problem. Thanks for sharing.

Regarding, your question, DPLL_VIDEO1/2 may or may not correspond to LCD1/2. The multiplexing logic allows this but it is not mandatory. Everything depends on the particular use-case.

Please see the diagram from the DSS chapter:

Regards,

Stan

0 samgyung zhang over 7 years ago in reply to Stanislav Stilyanov

Expert 1060 points

hi，Stanislav Stilyanov：

My project is based on dra722,dra722 do not have DPLL_VIDEO2,only have DPLL_VIDEO1.I have tried to make DPLL_VIDEO1 as lcd2's source clock,but the system corrupted,behaved like "kernel panic".Is that DPLL_VIDEO1 cannot served as the source clock of the LCD1 and LCD2 at the same time?can you help me to check some code in linux /drivers/video/fbdev/omap2/dss/dpi.c ?As following:

static struct pll_data *dpi_get_pll_data(enum omap_channel channel)
{

case OMAPDSS_VER_DRA72xx:
  switch (channel) {
  case OMAP_DSS_CHANNEL_LCD:
  //case OMAP_DSS_CHANNEL_LCD2:
  case OMAP_DSS_CHANNEL_LCD3:
   dss_ctrl_pll_set_control_mux(0, channel);
   return dss_dpll_get_pll_data(0);
  case OMAP_DSS_CHANNEL_LCD2:
   dss_ctrl_pll_set_control_mux(1, channel);//it chang 1 to 0,the system corrupted
   return dss_dpll_get_pll_data(1);
  default:
   return NULL;

0 Stanislav Stilyanov over 7 years ago in reply to samgyung zhang

TI__Genius 15120 points

DPLL_VIDEO1 to LCD1 and LCD2 simultaneously is a valid option. No restriction to that.
The issue is somewhere else.
- For example, you might need to change dss_dpll_get_pll_data(1); to 0 as well? It is a DPLL code , but which code is which DPLL?

- Also, do you know setting dss_ctrl_pll_set_control_mux(0, channel); parameter to 0 actually selects VIDEO1_DPLL? Register value corresponds, but is it implemented so in the function?

- Can you check VIDEO1_DPLL is actually locked and running?

Regards,
Stan

0 samgyung zhang over 7 years ago in reply to Stanislav Stilyanov

Expert 1060 points

hi,Stanislav Stilyanov :
Thanks for you patience.In fact ,i have changed dss_dpll_get_pll_data(1) to 0 as well before,please forgive my negligence.I know that setting dss_ctrl_pll_set_control_mux(0, channel); parameter to 0 actually selects VIDEO1_DPLL,that is exactly what i want to do.I want to make DPLL_VIDEO1 served as source clock for both lcd1 and lcd2 simultaneously .It is because the dra722 only have one DPLL_VIDEO.But after i do that,the system corrupted,is there some issues needed special handle?

0 Stanislav Stilyanov over 7 years ago in reply to samgyung zhang

TI__Genius 15120 points

Samgyung,
I'm not familiar with software for DSS and DPLL.
What I know is that LCD1, LCD2, and LCD3 can work from DPLL_VIDEO1. If mux is correct and DPLL is locked, I see no problem.
Can you print the mux register at address 0x4A00 2538 at the end of the function? (CTRL_CORE_DSS_PLL_CONTROL)

0 samgyung zhang over 7 years ago in reply to Stanislav Stilyanov

Expert 1060 points

hi,Stanislav Stilyanov

I don't know why VOUT1 and VOUT2 cannot share the DPLL_VIDEO1 at the same time,so i use the other method ,as you can see in the following,while i run "devmem2 0x4a002538",that i found that DSI1_A_CLK1 select the DPLL_VIDEO1,DSI1_B_CLK1 select RESERVED,after running dss_dumclocks.sh,i found the results like that "DPLL_VIDEO1→DSI1_A_CLK→LCD1_CLK，DSS_CLK→LCD2_CLK".From the Dra72x's TRM,i found the DSS CLOCK TREE's description,it indicated that DSS_CLK is also can be served as the source clock of all LCDs.But at the curren time ,two display screens are black.After running the dss_dumclock.sh.i found that both LCD1 and LCD2's clock is exactly right,and i found that weston has two outputs already .Why no outputs transfer to screen?

LCD1&LCD2_dss_dumclocks.txt

  653.53> =====================DSS clock script===================
  653.53> Dumps internal clocks and muxes of DSS
  653.55> 
  653.58> CTRL_CORE_DSS_PLL_CONTROL (0x4a002538) = 0x000002A6
  653.58> video1 PLL :  Enabled
  653.59> video2 PLL :  Disabled
  653.59> HDMI   PLL :  Disabled
  653.61> DSI1_A_CLK mux : DPLL Video1
  653.61> DSI1_B_CLK mux : DPLL video2
  653.61> DSI1_C_CLK mux : DPLL Video1
  653.61> 
  653.66> DSS_CTRL (0x58000040) = 0x00010001
  653.66>  2: LCD1 clk switch :  DSI1_A_CLK
  653.66>  3: LCD2 clk switch :  DSS clk
  653.66> 10: LCD3 clk switch :  DSS clk
  653.66>  1: func clk switch :  DSS clk
  653.66> 13: DPI1 output     :  LCD1
  653.66> 
  653.66> DSS_STATUS (0x5800005C) = 0x01408A82
  653.66> 
  653.69> DSI_CLK_CTRL (0x58004054) = 0x80004001
  653.69> 
  653.78> ========================================================
  653.80> Register dump for DPLL video1
  653.80> |----------------------------|
  653.80> | Address (hex) | Data (hex) |
  653.80> |----------------------------|
  653.80> | 0x58004300    | 0x00000018 |
  653.80> | 0x58004304    | 0x00002283 |
  653.80> | 0x58004308    | 0x00000000 |
  653.80> | 0x5800430C    | 0x00602600 |
  653.80> | 0x58004310    | 0x00616008 |
  653.80> | 0x58004314    | 0x00000000 |
  653.80> | 0x58004318    | 0x00000000 |
  653.81> | 0x5800431C    | 0x00000000 |
  653.81> | 0x58004320    | 0x00000000 |
  653.81> |----------------------------|
  653.81> Details for DPLL video1
  653.81> PLL status  :  Locked
  653.81> M4 hsdiv(1) :  Active
  653.81> M5 hsdiv(2) :  inactive
  653.81> M6 hsdiv(3) :  inactive
  653.81> M7 hsdiv(4) :  inactive
  653.81> 
  653.92> PLL_REGM   =  19
  653.94> PLL_REGN   =  0
  653.94> M4 DIV     =  3
  653.94> M6 DIV     =  0
  653.94> M7 DIV     =  0
  653.94> 
  653.94> Clock calculations (DPLL video1)
  653.94> sysclk = 20000000
  653.94> DCO clk = sysclk * 2 * REGM / (REGN + 1) = 760000000
  653.94> M4clk (clkcout1) = DCO clk / (M4 DIV + 1) = 190000000
  653.94> M6clk (clkcout3) = DCO clk / (M6 DIV + 1) = 0
  653.94> M7clk (clkcout4) = DCO clk / (M7 DIV + 1) = 0
  653.95> 
  653.95> ========================================================
  653.95> Clock O/P of MUXes
  654.05> DSI1_A_CLK :  190000000
  654.06> DSI1_B_CLK :  0
  654.06> DSI1_C_CLK :  0
  654.06> 
  654.11>  2: LCD1 clk :  190000000
  654.12>  3: LCD2 clk :  33000000
  654.12> 10: LCD3 clk :  33000000
  654.12>  1: func clk :  33000000
  654.12> 
  654.28> LCD1 logic clk(/ 1 ) :  190000000  pix clk(/ 5 ) :  38000000
  654.28> LCD2 logic clk(/ 1 ) :  33000000  pix clk(/ 1 ) :  33000000
  654.28> LCD3 logic clk(/ 4 ) :  8250000  pix clk(/ 1 ) :  8250000

static struct pll_data *dpi_get_pll_data(enum omap_channel channel)

{

case OMAPDSS_VER_DRA72xx:

switch (channel) {

case OMAP_DSS_CHANNEL_LCD:

//case OMAP_DSS_CHANNEL_LCD2:

case OMAP_DSS_CHANNEL_LCD3:

dss_ctrl_pll_set_control_mux(0, channel);

return dss_dpll_get_pll_data(0);

case OMAP_DSS_CHANNEL_LCD2:

dss_ctrl_pll_set_control_mux(1, channel);

return dss_dpll_get_pll_data(1);

default:

return NULL;

0 Venkat Mandela over 7 years ago in reply to samgyung zhang

TI__Expert 5770 points

Hi Samgyung,

Below are a set of patches to enable VOUT2 and VOUT1 simultaneously on DRA72x. These are only sanity tested on DRA72x EVM by alternatively placing VOUT1 and VOUT2 output on the LCD.

1, review.omapzoom.org/37626 , omapdss: pll: fix writing M6 & M7 divs
2, review.omapzoom.org/37627 , tmp:fix for VOUT1 + VOUT2 enablement to have LCD1 and LCD2
3, review.omapzoom.org/38278 , HACK: Enable M4 and M6 dividers always.
4, review.omapzoom.org/38279 , dra72: dts: enable vout2

Please use these as a reference and make the necessary changes on your kernel tree to enable VOUT2 and VOUT1 simultaneously.

regards,
Venkat

0 samgyung zhang over 7 years ago in reply to Venkat Mandela

Expert 1060 points

Hi,Venkat:

I am grateful that you respond me in detail,My project asked to display two LCDs with dra722,.It seems that only have LCD1 or only have LCD1 that everything is ok,but if i want both LCD1 and LCD2 to display at the same time,something unexpected happened that two display screens seems no output.The problem is still exist after i refer to your code.

in drivers/video/fbdev/omap2/dss/dpi.c,I feel so confused,

static struct pll_data *dpi_get_pll_data(enum omap_channel channel)

{

/*………………………………………………………………*/

case OMAPDSS_VER_DRA72xx:

switch (channel) {

case OMAP_DSS_CHANNEL_LCD:

//case OMAP_DSS_CHANNEL_LCD2:

case OMAP_DSS_CHANNEL_LCD3:

dss_ctrl_pll_set_control_mux(0, channel);//it means that LCD1 select DPLL_VIDEO1

return dss_dpll_get_pll_data(0);

case OMAP_DSS_CHANNEL_LCD2:

dss_ctrl_pll_set_control_mux(1, channel);

/*it means that LCD2 select RESERVE(CTRL_CORE_DSS_PLL_CONTROL),something that must be pointed out is if i change 1 to 0 here,just as the code like your patch,the system corrupted,but if i set 1 here,it product some errors like "[drm:omap_crtc_error_irq] *ERROR* lcd: errors: 00004000" in omap-crtc.c ,I have compared the omap-crtc.c with the evm sdk,it is almost the same.*/

return dss_dpll_get_pll_data(1);

default:

return NULL;

/*………………………………………………………………*/

}

can you give me some advise?Thank you very much!

0 Venkat Mandela over 7 years ago in reply to samgyung zhang

TI__Expert 5770 points

Hi Samgyung,

Do you have a DRA72x EVM with you? If yes, can you verify the 4 patches I shared on the EVM first to make sure both of us have the same results? I was able to have both VOUT1 and VOUT2 working simultaneously. I checked the output of VOUT2 by changing bits [17:16] of the register DSS_CTRL(0x58000040) to place the output of VOUT2 on VOUT1. You can use omapconf read/write commands to try this out.

What is your test case for the display? Are you running any applications or just booting to prompt?

regards,
Venkat

0 samgyung zhang over 6 years ago in reply to Venkat Mandela

Expert 1060 points

Hi,venkat
Sorry for too late to respond,i was on my business last two months.Thanks for your great work,it is all my problem.Now the two lcds work simultaneously.Thank you very much,hope you have a good day!

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Linux/DRA722: dra722 vout2 cannot enable lcd2 output