• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 101 subscribers
  • Views 361 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRA744: DRA744 HCSL port

DANIELE COZZI
Expert 4070 points
Part Number: DRA744
Other Parts Discussed in Thread: CDCM9102

My customer is developing a cluster using our JAC DRA744   and they need to connect the DRA744   with a WiFi module 
   the Wifi module  is operating with LVPECL  ; the Jac DRA744  port is an HCSL , in order to manage the two different specification (modem  LVPECL and DRA744 HCSL) I have proposed CDCM9102 But , question is :  do we need to add a buffer form Jac DRA744 port to the modem?  Or the fan out of Jac DRA744 is able to manage the interface w/o any  external buffer ? The connection lenght is 200mm
 , but I need your help to figure out if we have to add an external buffer

I need also another information on top of the here below request.
>    Is the 100Mhz clock available for external clock driver ?
>    I am asking since I am going to decide what is the best solution for the external clock driver
>

  • 0
    TI__Genius 15120 points
    Hi Daniele,
    I'm not sure I fully understand your question. CDCM9102 is already a clock generator/driver. It has 2 outputs: one to PCIe slot/device; one to the DRA744. DRA744 will accept the clock in this case, not generating it. No buffers required between CDCM9102 and SoC.

    Regards,
    Stan