Linux/DRA750: J6 boot up stucking in "get_ram_size() successful<<sdram_init()"

Ren Bowei

Part Number: DRA750
Other Parts Discussed in Thread: CCSTUDIO

Tool/software: Linux

Dear all,

We have custom daughter board + custom DRA752 CPU module board with uboot 2014.07 in glsdk 7.03.00.00.3 , but some our CPU modules which filter out by our MP line are bad.

Because those CPU modules can not boot up successfully , the boot log only print 2 lines.

U-Boot SPL 2014.07 (Apr 26 2017 - 16:16:36)
DRA752-GP ES2.0

So I add some debug message in SPL code , I found the SPL stuck in the function "void s_init(void)" like below:

arch/arm/cpu/armv7/omap-common/hwinit-common.c
void s_init(void)
{
	/*
	 * Save the boot parameters passed from romcode.
	 * We cannot delay the saving further than this,
	 * to prevent overwrites.
	 */
#ifdef CONFIG_SPL_BUILD
	save_omap_boot_params();
#endif
	printf("before init_omap_revision\n");
	init_omap_revision();
	
	printf("before hw_data_init\n");
	hw_data_init();

#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SPI_PROD_OS_BOOT)
	if (((get_sysboot_value() & SYSBOOT_TYPE_MASK) == SYSBOOT_TYPE_PROD) &&
	    ((get_sysboot_value() == SYS_BOOT_QSPI_1_PROD) ||
	     (get_sysboot_value() == SYS_BOOT_QSPI_4_PROD))) {
		gd->arch.omap_boot_params.omap_bootmode = SPI_MODE_PROD;
	}
#endif

#ifdef CONFIG_SPL_BUILD
	if (warm_reset() &&
	    (is_omap44xx() || (omap_revision() == OMAP5430_ES1_0)))
		force_emif_self_refresh();
#endif
	printf("before watchdog_init\n");
	watchdog_init();
	printf("before set_mux_conf_regs\n");
	set_mux_conf_regs();
#ifdef CONFIG_SPL_BUILD
	printf("before srcomp_enable\n");
	srcomp_enable();
	printf("before setup_clocks_for_console\n");
	setup_clocks_for_console();

	gd = &gdata;

	printf("before preloader_console_init\n");
	preloader_console_init();
	
	printf("before do_io_settings\n");
	do_io_settings();
#endif
	printf("before prcm_init\n");
	prcm_init();
#ifdef CONFIG_SPL_BUILD
#ifdef CONFIG_BOARD_EARLY_INIT_F
	printf("before board_early_init_f\n");
	board_early_init_f();
#endif
	/* For regular u-boot sdram_init() is called from dram_init() */
	printf("before sdram_init\n");
	sdram_init();
#endif
}

All log including debug message what we added as below:

U-Boot SPL 2014.07 (Apr 26 2017 - 16:16:36)
DRA752-GP ES2.0
spl_mmc_load_image
reading dra7-evm.dtb
spl_load_image_fat_os: error reading image dra7-evm.dtb, err - -1
reading u-boot.img
reading u-boot.img


U-Boot 2014.07 (Apr 26 2017 - 16:16:36)                   
                                                          
CPU  : DRA752-GP ES2.0                                    
Board: DRA7xx                                             
I2C:   ready                                              
DRAM:  2 GiB
MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1, OMAP SD/MMC: 2
Using default environment

serial# not set, setting...
Target spinup took 0 ms.
AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
flags: 64bit ncq stag pm led clo only pmp pio slum part ccc apst 
scanning bus for devices...

U-Boot SPL 2014.07 (Apr 26 2017 - 16:16:36)
DRA752-GP ES2.0

U-Boot SPL 2014.07 (Mar 21 2017 - 11:51:30)
DRA752-GP ES2.0
before do_io_settings
before prcm_init
        |-before enable_basic_clocks
Enable clock domain - 4a009700
Enable clock domain - 4a009300
Enable clock domain - 4a008b00
Enable clock domain - 4a008d00
Enable clock domain - 4a0093c0
Enable clock domain - 4a008700
Enable clock module - 4a008728
Enable clock module - 4a008b30
Enable clock module - 4a008b38
Enable clock module - 4a008d20
Enable clock module - 4ae07838
Enable clock module - 4a009760
Enable clock module - 4a009768
Enable clock module - 4a009770
Enable clock module - 4a009778
Enable clock module - 4a009780
Enable clock module - 4a009810
Enable clock module - 4a009818
Enable clock module - 4a008778
Enable clock module - 4a008780
Enable clock module - 4ae07840
Enable clock module - 4a009328
Enable clock module - 4a009330
Enable clock module - 4a009738
Enable clock module - 4ae07830
Enable clock module - 4a009850
Enable clock module - 4a0097a0
Enable clock module - 4a0093d0
Enable clock module - 4a009838
Enable clock domain - 4a009700
Enable clock domain - 4a009300
Enable clock domain - 4a008b00
Enable clock domain - 4a008d00
Enable clock domain - 4a0093c0
Enable clock domain - 4a008700
        |-before timer_init
        |-before scale_vcores
                |-before vcores->core
optimize_vcore_voltage:efuse 0x4a0025f4 bits=16 Vnom=1030, using efuse value 1045
                |-before core
do_scale_vcore: volt - 1045 offset_code - 0x3d
                |-before recalibrate_iodelay
                        |-before __recalibrate_iodelay
                                |-before calibrate_iodelay
                                |-before isolate_io
                                        |- isolate = 1
                                        |-  wait_on_value1C�BBBBB�K��wait_on_value2
IODELAY: IO delay recalibration successfully completed
                |-before vcores->mpu
optimize_vcore_voltage:efuse 0x4a003b20 bits=16 Vnom=1090, using efuse value 1070
                |-before mpu
do_scale_vcore: volt - 1070 offset_code - 0x3f
                |-before abb_setup
                |-before mm
                |-before mm
                |-before gpu
optimize_vcore_voltage:efuse 0x4a003b10 bits=16 Vnom=1250, using efuse value 1075
                |-before gpu
do_scale_vcore: volt - 1075 offset_code - 0x40
                |-before eve
optimize_vcore_voltage:efuse 0x4a0025e0 bits=16 Vnom=1060, using efuse value 990
                |-before eve
do_scale_vcore: volt - 990 offset_code - 0x37
                |-before iva
optimize_vcore_voltage:efuse 0x4a0025cc bits=16 Vnom=1060, using efuse value 1005
                |-before iva
do_scale_vcore: volt - 1005 offset_code - 0x39
 |-before setup_dplls
setup_dplls

 core Dpll locked, but not for ideal M = 277,N = 4 values, current values are M = 133
0,N= 23
 before core[4a005120] Dpll wait_for_lock 
Core DPLL configured

 per Dpll locked, but not for ideal M = 20,N = 0 values, current values are M = 1280,
N= ��jRI���KW$�Y�+MX��8140] Dpll wait_for_lock 
PER DPLL locked

 mpu Dpll locked, but not for ideal M = 625,N = 11 values, current values are M = 147
0,N= 23
 before mpu[4a005160] Dpll wait_for_lock 
MPU DPLL locked

 before usb[4a008180] Dpll wait_for_lock 

 before ddr[4a005210] Dpll wait_for_lock 

 before gmac[4a0052a8] Dpll wait_for_lock 
 |-before setup_warmreset_time
before board_early_init_f
before sdram_init
>>sdram_init()
in_sdram = 0
>>do_sdram_init() 4c000000
<<do_sdram_init() 4c000000
>>do_sdram_init() 4d000000
<<do_sdram_init() 4d000000
 size_prog = 7f000000 
base=80000000 , maxsize=40000000 , cnt=10000000
i=28
get_ram_size() successful<<sdram_init()

Could you give us some direction to debug it ? ( it should be h/w issue , but we want to know which part is NG )

Thank you for your help!

Best Regards,

Bowei Ren

over 6 years ago

0 Mariya Petkova over 6 years ago

TI__Expert 4885 points

Hi,

Experts are notified about your query.

Regards,
Mariya

0 Ravi B over 6 years ago in reply to Mariya Petkova

TI__Expert 7885 points

Whether timing parameters for the specific DDR used in custom board has been configured properly. DMM LISA map register are set properly ?

refer to board/ti/dra7xx/evm.c as reference. refer emif_get_dmm_regs() and emif_get_reg_dump() function.

Regards

Ravi

0 Ren Bowei over 6 years ago in reply to Ravi B

Intellectual 650 points

Hi Ravi,

In fact, only a few CPU module have this problem and these CPU modules are filter out from our production line. So we would like to know what happened on these CPU modules.
Could you give me some direction to debug it? or where we need to add debug messages?

Best Regards,
Bowei Ren

0 Ravi B over 6 years ago in reply to Ren Bowei

TI__Expert 7885 points

What is the customer name ?

Can you provide more details on exact CPU part number.

How many such CPU part has problem?.

Whether problem is related to custom board or CPU part or DDR memory part.

Whether non-working board works if you replace the working CPU part ?

Regards

Ravi

0 Ren Bowei over 6 years ago in reply to Ravi B

Intellectual 650 points

Hi

The customer name is Harman.
We have three CPU modules that have the same error feature.
For DDR memory part, we have tested DDR stress test by CCstudio.
For custom board, we have checked all power as close to the CPU as possible and they are all good.
So we suspect point is CPU part at present stage. But we don't know what happened on this CPU module.

Best Regards,
Bowei

0 Ravi B over 6 years ago in reply to Ren Bowei

TI__Expert 7885 points

Bowei

You need to debug further, put prints, what is exact place or instruction the hang is seen, and consistent of the issue.

Only the 3 CPU modules exhibit this issue, as i understand you do not any issue with other working CPU module with same image & DDR memory?

Regard

Ravi

0 Ren Bowei over 6 years ago in reply to Ravi B

Intellectual 650 points

Hi Ravi,

Yes, the image and DDR memory are the same both working and non-working board.
As I know, the boot flow should be executed main function (arch/arm/lib/crt0.S) after sdram_init (arch/arm/cpu/armv7/omap-common/emif-common.c) finished.
Do you have any suggestions that I can add debug message between sdram_init and main function?

BRs,
Bowei Ren

0 Ravi B over 6 years ago in reply to Ren Bowei

TI__Expert 7885 points

Bowei Ren

You have mentioned, only 3 CPU sample shown this issue right? So the issue not seen in other working samples ? I am right?

I feel you should connect JTAG and debug, to check where exactly its hanging.

Regards

Ravi

0 Ren Bowei over 6 years ago in reply to Ravi B

Intellectual 650 points

Hi Ravi,

Yes, you are right.
To use JTAG to debug by CCS. That's also a good idea. But how to use CCS to debug this issue? or could you provide some related documents to me?
In fact, I have executed DDR stress test by CCS, and the result is pass.

Best Regards,
Bowei Ren

0 Ren Bowei over 6 years ago in reply to Ren Bowei

Intellectual 650 points

Hi Ravi,

I tried to use CCS to do debug further, I refered to CCS user guide and used Cortex-A15 PC Trace.

I need to know which process step is haug when the error encountered.

But I get the error message as below when I execute PC Trace:

Do you have any idea?

BTW, PC Trace can help me to understand the issue what discussed in the previous post?

Thank you for your support!

Best Regards,

Bowei

0 Ravi B over 6 years ago in reply to Ren Bowei

TI__Expert 7885 points

Bowei

Please don't load the GEL file, remove the GEL file and try to connect to A15 through CCS.

Regards

Ravi

0 Ren Bowei over 6 years ago in reply to Ravi B

Intellectual 650 points

Hi Ravi,

I don't load any GEL file.
Just connect to target (cortexA15_0) and execute "PC Trace".

Best Regards,
Bowei

0 Ren Bowei over 6 years ago in reply to Ren Bowei

Intellectual 650 points

Hi Ravi,

Do I need to load any script after connecting to target?

Best Regards,
Bowei

0 Ravi B over 6 years ago in reply to Ren Bowei

TI__Expert 7885 points

Bowei

When you are connecting CCS to debug u-boot/kernel, don't load the GEL file. You can load the u-boot symbol file once you are able to connect to
target.

Regards
Ravi

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Linux/DRA750: J6 boot up stucking in "get_ram_size() successful<<sdram_init()"