Other Parts Discussed in Thread: CCSTUDIO
Tool/software: Linux
Dear all,
We have custom daughter board + custom DRA752 CPU module board with uboot 2014.07 in glsdk 7.03.00.00.3 , but some our CPU modules which filter out by our MP line are bad.
Because those CPU modules can not boot up successfully , the boot log only print 2 lines.
U-Boot SPL 2014.07 (Apr 26 2017 - 16:16:36) DRA752-GP ES2.0
So I add some debug message in SPL code , I found the SPL stuck in the function "void s_init(void)" like below:
arch/arm/cpu/armv7/omap-common/hwinit-common.c void s_init(void) { /* * Save the boot parameters passed from romcode. * We cannot delay the saving further than this, * to prevent overwrites. */ #ifdef CONFIG_SPL_BUILD save_omap_boot_params(); #endif printf("before init_omap_revision\n"); init_omap_revision(); printf("before hw_data_init\n"); hw_data_init(); #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SPI_PROD_OS_BOOT) if (((get_sysboot_value() & SYSBOOT_TYPE_MASK) == SYSBOOT_TYPE_PROD) && ((get_sysboot_value() == SYS_BOOT_QSPI_1_PROD) || (get_sysboot_value() == SYS_BOOT_QSPI_4_PROD))) { gd->arch.omap_boot_params.omap_bootmode = SPI_MODE_PROD; } #endif #ifdef CONFIG_SPL_BUILD if (warm_reset() && (is_omap44xx() || (omap_revision() == OMAP5430_ES1_0))) force_emif_self_refresh(); #endif printf("before watchdog_init\n"); watchdog_init(); printf("before set_mux_conf_regs\n"); set_mux_conf_regs(); #ifdef CONFIG_SPL_BUILD printf("before srcomp_enable\n"); srcomp_enable(); printf("before setup_clocks_for_console\n"); setup_clocks_for_console(); gd = &gdata; printf("before preloader_console_init\n"); preloader_console_init(); printf("before do_io_settings\n"); do_io_settings(); #endif printf("before prcm_init\n"); prcm_init(); #ifdef CONFIG_SPL_BUILD #ifdef CONFIG_BOARD_EARLY_INIT_F printf("before board_early_init_f\n"); board_early_init_f(); #endif /* For regular u-boot sdram_init() is called from dram_init() */ printf("before sdram_init\n"); sdram_init(); #endif }
All log including debug message what we added as below:
U-Boot SPL 2014.07 (Apr 26 2017 - 16:16:36) DRA752-GP ES2.0 spl_mmc_load_image reading dra7-evm.dtb spl_load_image_fat_os: error reading image dra7-evm.dtb, err - -1 reading u-boot.img reading u-boot.img U-Boot 2014.07 (Apr 26 2017 - 16:16:36) CPU : DRA752-GP ES2.0 Board: DRA7xx I2C: ready DRAM: 2 GiB MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1, OMAP SD/MMC: 2 Using default environment serial# not set, setting... Target spinup took 0 ms. AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl SATA mode flags: 64bit ncq stag pm led clo only pmp pio slum part ccc apst scanning bus for devices... U-Boot SPL 2014.07 (Apr 26 2017 - 16:16:36) DRA752-GP ES2.0 U-Boot SPL 2014.07 (Mar 21 2017 - 11:51:30) DRA752-GP ES2.0 before do_io_settings before prcm_init |-before enable_basic_clocks Enable clock domain - 4a009700 Enable clock domain - 4a009300 Enable clock domain - 4a008b00 Enable clock domain - 4a008d00 Enable clock domain - 4a0093c0 Enable clock domain - 4a008700 Enable clock module - 4a008728 Enable clock module - 4a008b30 Enable clock module - 4a008b38 Enable clock module - 4a008d20 Enable clock module - 4ae07838 Enable clock module - 4a009760 Enable clock module - 4a009768 Enable clock module - 4a009770 Enable clock module - 4a009778 Enable clock module - 4a009780 Enable clock module - 4a009810 Enable clock module - 4a009818 Enable clock module - 4a008778 Enable clock module - 4a008780 Enable clock module - 4ae07840 Enable clock module - 4a009328 Enable clock module - 4a009330 Enable clock module - 4a009738 Enable clock module - 4ae07830 Enable clock module - 4a009850 Enable clock module - 4a0097a0 Enable clock module - 4a0093d0 Enable clock module - 4a009838 Enable clock domain - 4a009700 Enable clock domain - 4a009300 Enable clock domain - 4a008b00 Enable clock domain - 4a008d00 Enable clock domain - 4a0093c0 Enable clock domain - 4a008700 |-before timer_init |-before scale_vcores |-before vcores->core optimize_vcore_voltage:efuse 0x4a0025f4 bits=16 Vnom=1030, using efuse value 1045 |-before core do_scale_vcore: volt - 1045 offset_code - 0x3d |-before recalibrate_iodelay |-before __recalibrate_iodelay |-before calibrate_iodelay |-before isolate_io |- isolate = 1 |- wait_on_value1C�BBBBB�K��wait_on_value2 IODELAY: IO delay recalibration successfully completed |-before vcores->mpu optimize_vcore_voltage:efuse 0x4a003b20 bits=16 Vnom=1090, using efuse value 1070 |-before mpu do_scale_vcore: volt - 1070 offset_code - 0x3f |-before abb_setup |-before mm |-before mm |-before gpu optimize_vcore_voltage:efuse 0x4a003b10 bits=16 Vnom=1250, using efuse value 1075 |-before gpu do_scale_vcore: volt - 1075 offset_code - 0x40 |-before eve optimize_vcore_voltage:efuse 0x4a0025e0 bits=16 Vnom=1060, using efuse value 990 |-before eve do_scale_vcore: volt - 990 offset_code - 0x37 |-before iva optimize_vcore_voltage:efuse 0x4a0025cc bits=16 Vnom=1060, using efuse value 1005 |-before iva do_scale_vcore: volt - 1005 offset_code - 0x39 |-before setup_dplls setup_dplls core Dpll locked, but not for ideal M = 277,N = 4 values, current values are M = 133 0,N= 23 before core[4a005120] Dpll wait_for_lock Core DPLL configured per Dpll locked, but not for ideal M = 20,N = 0 values, current values are M = 1280, N= ��jRI���KW$�Y�+MX��8140] Dpll wait_for_lock PER DPLL locked mpu Dpll locked, but not for ideal M = 625,N = 11 values, current values are M = 147 0,N= 23 before mpu[4a005160] Dpll wait_for_lock MPU DPLL locked before usb[4a008180] Dpll wait_for_lock before ddr[4a005210] Dpll wait_for_lock before gmac[4a0052a8] Dpll wait_for_lock |-before setup_warmreset_time before board_early_init_f before sdram_init >>sdram_init() in_sdram = 0 >>do_sdram_init() 4c000000 <<do_sdram_init() 4c000000 >>do_sdram_init() 4d000000 <<do_sdram_init() 4d000000 size_prog = 7f000000 base=80000000 , maxsize=40000000 , cnt=10000000 i=28 get_ram_size() successful<<sdram_init()
Could you give us some direction to debug it ? ( it should be h/w issue , but we want to know which part is NG )
Thank you for your help!
Best Regards,
Bowei Ren