• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 2 answers
  • Subscribers 101 subscribers
  • Views 767 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Compiler/DRA756: Could you please introduce the hardware leveling principle at J6?

Tao Han
Expert 5825 points
Part Number: DRA756

Tool/software: TI C/C++ Compiler

Hi expert:

My customer about J6 DDR3 memory control have some problem, Please give us some suggest about it?

Question 1: At TRM 15.3.4.8 said that J6 use hardware leveling. But it did not introduce the hardware leveling method. Does DDR3 hardware leveling will write special data pattern to DDR IC and read back the data, to fill the Writing leveling register, Read data eye leveling register and Read DQS leveling register? Whether hardware leveling will fill Max, Min, Optimum value. ( Register at 0x4C00 0230 0x4C00 0280 0x4C00 0258 0x4C00 0208 )

Question 2: Does we have document about how to simulate the DDR3 eye pattern for DDR3? Customer want to simulate DDR3 signal integrity but they did not know how to use IBIS module.

I can find software leveling work method at AvatarEMIFtool. but hardware leveling did not give us clear description.

Best Regards!

Han Tao 

  • 0
    TI__Mastermind 42515 points
    Hi,

    I have forwarded your question to DDR expert.

    Regards,
    Yordan
  • 0
    TI__Mastermind 26655 points
    Hi,

    Q1: Hardware leveling is done entirely between the EMIF PHY and the DDR memory. The write leveling concept is described in detail in section 4.8 of the DDR3 JEDEC standard (JESD79-3F). For read leveling, the PHY enables the DDR's multi-purpose register (MPR) to readout a pre-defined pattern. The MPR is also described in the DDR3 JEDEC standard. Hardware leveling does not populate the EMIF_EXT_PHY_CONTROL_* registers; however, the optimal values returned by hardware leveling can be read from the EMIF_PHY_STATUS_* registers. If hardware leveling is enabled, then the PHY will use the DLL ratio values obtained from hardware leveling, rather than from the EMIF_EXT_PHY_CONTROL_* registers.

    Q2: I am not aware of any documents that TI provides describing how to simulate the EMIF interface; however, third party software can be used to simulate the EMIF interface using the IBIS model.

    Best regards,
    Kevin
  • 0 in reply to Kevin S
    TI__Expert 5825 points

    Hi Kevin:

    Thanks for your suggest.

    About Q2: IBIS module i find a APN about it. Maybe other people can use this APN.(www.ti.com/.../spra839a.pdf)

    Best Regards!

    han tao