DRA718: Does J6 entry power up sequence the delay time have limitied?

Tao Han

Expert 5825 points

Part Number: DRA718
Other Parts Discussed in Thread: LP8733

Hi experts:

Our customer design J6 entry board with LP8733 + separate circuit.

Now the power up sequence and power down sequence match datasheet request. But the power up sequence.

Vdda_usb3 power delay behind vdd_dsp about 1.5ms. The vddshv1,3,4 11 delay to vdd_usb3 more than 1ms.

J6 entry the power up delay time have limited or not? Every power rail delay more than 1ms can meet request?

Best Regards!

Han Tao

over 6 years ago

0 Lyudmila Kamenova over 6 years ago

TI__Intellectual 1285 points

Hi,

The question is forwarded to a HW expert.

Best regards
Lucy

0 Yordan Kamenov over 6 years ago in reply to Lyudmila Kamenova

TI__Mastermind 42515 points

Hi Tao,

just to inform you: there might be some delays in answering this query, caused by TI's office in Sugar Land being closed because of floodings.

Regards,
Yordan

0 Kevin Lavery over 6 years ago

TI__Genius 14900 points

Han,

It is necessary to preserve the order of these voltage ramps, and for the power-up sequence delays of a few milliseconds are acceptable from a device perspective.

From the application-view, the delays must also meet the application's boot-time requirements.

As you mentioned in the original submission, the proper sequence must be maintained on power-down as well.

Best regards,

Kevin

0 Tao Han over 6 years ago in reply to Kevin Lavery

TI__Expert 5825 points

Hi Kevin:

Thanks for help us confirm it.
We will insure customer power up every rail sequence meet Data Manual request.
Looks like every rail delay about 1ms is acceptable for J6 entry.
Best Regards!
Han Tao

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DRA718: Does J6 entry power up sequence the delay time have limitied?