DRA72XEVM: Workload Measurment without SYS/BIOS on DRA72XEVM

Paul Klose

Part Number: DRA72XEVM

Hello,

i'm trying to run the workload measurment from the "chip support library" in the pdk_C6670_1_1_2_6. Does this work?

First i tryed the "chip support library" from pdk_dra7xx_1_0_8, but the ti.csl.ae66 doesn't support/include the functions for workload Measurment (emp.: CSL_tscEnable).

I can measure the workload with the pdk_C6670_1_1_2_6, but the workload is to high. The workload is 4 times or more higher than the TMS320C6670.

My main questions are:

How can i measure the workload of the C66 DSP inside the DRA72XEVM without any Linux and RTOS?

Also, which settings are important for the optimal core speed? (I enabled the -mt flag and complie my code with -O3, but the core is still slow. )

Can you send me a linker command file with the best memory mapping?

best regards

Paul

over 6 years ago

0 Yordan Kamenov over 6 years ago

TI__Mastermind 42515 points

Hi Paul,

I have forwarded your question to PDK experts.

Regards,
Yordan

0 Stephen Molfetta over 6 years ago in reply to Yordan Kamenov

TI__Expert 5725 points

Hi Paul,

You are correct that the function CSL_tscEnable isn't currently supported in the C66x CSL library from the dra7xx pdk. It is possible to enable this by adding dra72x to the list of cores in <pdk_dir>/ti/csl/src/ip/tsc/src_files_tsc.mk and rebuilding the library. Otherwise, it is straightforward use the C66x CPU clock counters (TSCH/TSCL) provided by the C6x toolchain.

Let me point you to few resources:

http://www.ti.com/lit/an/sprabf2/sprabf2.pdf

Regarding a linker command file with "the best memory mapping", there is no single best method. This is all dependent on several the application constraints. Please take a look at these resources and let me know if this helps with your problem. Otherwise, I will need to understand your code better in order to give you more specific guidance.

Thanks,
Stephen

0 Stephen Molfetta over 6 years ago in reply to Stephen Molfetta

TI__Expert 5725 points

I'm not sure what happened when posting the links, but the links and descriptions didn't show up. Let me try again

http://www.ti.com/lit/an/sprabf2/sprabf2.pdf provides a primer on C6000 optimization and gives a list of key techniques used to cover most optimization problems. Appendix B.1 also shows how to use the TSC registers to profile a piece of code
http://www.ti.com/lit/an/spra666/spra666.pdf is a bit more advanced and gives a much more thorough treatment of optimization to help achieve even higher performance
http://processors.wiki.ti.com/index.php/C6000_Compiler:_Recommended_Compiler_Options is a handy list of compiler options and explains how to balance speed versus other factors like code size, debugability, etc.

Thanks,
Stephen

0 Paul Klose over 6 years ago in reply to Stephen Molfetta

Intellectual 260 points

Thanks for your help, now it works fine. I can use also both csl libs from pdk_dra7xx_1_0_8 and pdk_C6670_1_1_2_6. Both are working fine and i get a similar result from the DRA72x now.

I red a lot inside the datasheets from you and for now i'm not sure about my walkthrough that i did. So i can't say why it works now. Is a bit magic to me and strange.

Maybe i did some correct settings inside my project now or it was somthing different inside my code and not the cache.

best regards

Paul

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DRA72XEVM: Workload Measurment without SYS/BIOS on DRA72XEVM