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DRA746: What's the correct frequency of APLL_PCIE output signal CLKOUTX2_VCO_LDO_DIV?

Part Number: DRA746

A customer project based on the DRA74x SoC is using the PCIe interface for communication to another MPU. The PCIe interface is working without any issues in this configuration, but when using the Frequency Analyzer of the Clock Tree Tool, a frequency error is reported for the clock signal PCIE_PHY_DIV_GCLK of both PCIE sub-systems. The basic question is now if this frequency violation is true.

The TRM description of the PCIe PHY APLL Output Clock Configuration requires bit CLKDIV_BYPASS in register CM_CLKMODE_APLL_PCIE to be set to '1' which disables the divider by 2 for the PCIE_PHY_DIV_GCLK clock signal, resulting in both APLL_PCIE output clocks (PCIE_PHY_GCLK as well as PCIE_PHY_DIV_GCLK) having the identical frequency of 2.5GHz.

and

That results in a violation of the maximum supported clock frequency of 1250MHz for PCIE_PHY_DIV_GCLK as defined in the DM.

Can somebody clarify this conflict or is the customer really using the PCIeSS out of spec?

Best regards,

Manfred

  • All of the inserted pictures were invisible again, so I try to insert them now differently.

    A customer project based on the DRA74x SoC is using the PCIe interface for communication to another MPU. The PCIe interface is working without any issues in this configuration, but when using the Frequency Analyzer of the Clock Tree Tool, a frequency error is reported for the clock signal PCIE_PHY_DIV_GCLK of both PCIE sub-systems. The basic question is now if this frequency violation is true.

    The TRM description of the PCIe PHY APLL Output Clock Configuration requires bit CLKDIV_BYPASS in register CM_CLKMODE_APLL_PCIE to be set to '1' which disables the divider by 2 for the PCIE_PHY_DIV_GCLK clock signal, resulting in both APLL_PCIE output clocks (PCIE_PHY_GCLK as well as PCIE_PHY_DIV_GCLK) having the identical frequency of 2.5GHz.

    and

    That results in a violation of the maximum supported clock frequency of 1250MHz for PCIE_PHY_DIV_GCLK as defined in the DM.

    Can somebody clarify this conflict or is the customer really using the PCIeSS out of spec?

    Best regards,

    Manfred

  • ,

    Can you attach here or email me a CTT register dump for me to replicate. From the get-go should be OK from tool's perspective, I can say the CTT is just comparing frequencies from DM vs your configured ones. Question is, is the DM restriction valid or should it be removed based on the current PCIE implementation (as mention in the chapter)? Most of the "_DIV" clocks in that table are always divided, so maybe the PCIE_DIV one is just an exception and therefore the wrong restriction.

    thanks
    Alex
  • Hi Alex,

    you can use the attached 'Processor_SDK_03_04_00_03.rd1' file as an example input for CTT to reproduce this frequency error detection. I'm using the latest CTT-Automotive version (v1.0.0.5).

    Processor_SDK_03_04_00_03.7z

    Beside this detected frequency error, I also found several problems with the APLL_PCIE and even the DPLL_PCIE_REF model. Maybe you've a chance to look into this as well.

    • To my understanding the APLL_PCIE requires a 100MHz reference clock to generate the 2.5GHz clock signals required for the PCIe PHY. This 100MHz input clock from either the DPLL_PCIE (output signal PCIE_REF_CLK) or an externally provided PCIe REFCLK is used. The selection between these two possible clock sources is done by bit REFCLK in register CM_CLKMODE_APLL_PCIE.
      • In the example configuration you will see a 100MHz clock frequency for the DPLL_PCIE_REF output signal CLKOUT_M2, but 1500MHz for CLKOUT_M2_LDO. Why is that the case? This DPLL is a type B PLL and the generated output clocks should both be divided by M2. 1500MHz as reference clock signal for the APLL_PCIE doens't make much sense.
      • The APLL_PCIE model doens't react on changes of the REFSEL bit in register CM_CLKMODE_APLL_PCIE, means it's not possible to select the PCIESREF_ACS_CLK signal as reference clock for the APLL.
      • All of the APL_PCIE output clocks are directly following the PCIE_REF_CLK frequency, means there's no PLL functionality which multiplies a 100MHz reference input clock by 25 to generate the needed 2.5GHz output clocks.

    Best regards,

    Manfred

  • Hi, ,

    I will file an internal Jira ticket for CTT models (will sent you the number by mail).

    Will discussed with DM team about the PCIE_PHY_DIV_GCLK issue. It seems that the confusion became from the name, as Alex wrote.
    As per PCIe TRM chpater:
    "The second divided clock PCIE_PHY_DIV_GCLK is delivered after passing the main APLL output clock
    through a by-2-divider (with baypass capabilities) and is outputed on CLKVCOLDO_DIV output. This clock
    is fed to the PCIe PHY TX modules and delivers sinchronization of the TX modules in two lane mode."

    Regads,
    Mariya
  • ,

    As per 26.4.4.3.2.1 PCIe PHY Subsystem Input Clocks chapter:

    "The high speed clock APLL_PCIE_REF.CLKVCOLDO_DIV (PCIE_PHY_DIV_GCLK) could be divided by 2 on two places, in the APLL_PCIE own by-2-divider or in the PHY_TX internal by-2-divider. These dividers support force-bypass mode where the divider is bypassed and no division is performed. The dividers of the APLL_PCIE and of the PHY_TX are cascaded: one divider should always be bypassed, and the other active. For one lane operation the APLL_PCIE divider could be force-baypassed and only internal PCIe_PHY divider to be active."

    So, there is no problem to supply PCIeSS with 2.5GHz if the internal divider is set. I suppose that your client activated the internal divider.

    The table in the DM can't be modified because the PCIEPHY_CLK_DIV shows the maximum operating frequency of the IP. And it is 1.25GHz. The clock at the border of the IP can be 2.5GHz and 1.25GHz.

    Regards,
    Mariya