A customer project based on the DRA74x SoC is using the PCIe interface for communication to another MPU. The PCIe interface is working without any issues in this configuration, but when using the Frequency Analyzer of the Clock Tree Tool, a frequency error is reported for the clock signal PCIE_PHY_DIV_GCLK of both PCIE sub-systems. The basic question is now if this frequency violation is true.
The TRM description of the PCIe PHY APLL Output Clock Configuration requires bit CLKDIV_BYPASS in register CM_CLKMODE_APLL_PCIE to be set to '1' which disables the divider by 2 for the PCIE_PHY_DIV_GCLK clock signal, resulting in both APLL_PCIE output clocks (PCIE_PHY_GCLK as well as PCIE_PHY_DIV_GCLK) having the identical frequency of 2.5GHz.
and
That results in a violation of the maximum supported clock frequency of 1250MHz for PCIE_PHY_DIV_GCLK as defined in the DM.
Can somebody clarify this conflict or is the customer really using the PCIeSS out of spec?
Best regards,
Manfred