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Linux/DRA745: How to config DRA745 with 3GB DDR??

Part Number: DRA745

Tool/software: Linux

I have custom board of DRA745 SoC with 3GB DDR.

The memory layout is 

EMIF 1 : 1GB x 2

EMIF 2: 512MB x 2

static const struct dmm_lisa_map_regs lisa_map_dra7_3GB = {

.dmm_lisa_map_0 = 0x00000000,
.dmm_lisa_map_1 = 0x80700100,   // EMIF-1 own 2GB start address  at 0x8000_0000
.dmm_lisa_map_2 = 0x??600280,  // EMIF-2 SYS_ADDR start address at  0x1_0000_0000 out of range?????
.dmm_lisa_map_3 = 0xFF020100,
.is_ma_present = 0x1
};

How to config the EMIF-2 sys_addr field????

Thx a lot.

  • Is someone can give me direction?....

  • Hi,
    I was wondering if you got a chance to refer this document at www.ti.com/.../spraca1.pdf
    Also please refer the EMIF configuration tool referred in that document.

    Regards,
    Somnath
  • Hi Somnath,
    Thx ur suggestion.
    I have already refer this document and the EMIF configuration tool.

    In current i can use only EMIF-1(2GB) or only EMIF-2(1GB) seprately that means the DDR timming parameters is correct.

    But i have some trouble when i use both EMIF-1 and EMIF-2 concurrent.

    Below is my dmm_lisa_map register setting.
    =============================================================
    static const struct dmm_lisa_map_regs lisa_map_dra7_3GB = {

    .dmm_lisa_map_0 = 0x80600200,
    .dmm_lisa_map_1 = 0xC0700120,
    .dmm_lisa_map_2 = 0x00000000,
    .dmm_lisa_map_3 = 0x00000000,
    .is_ma_present = 0x1

    };


    Using this setting can boot success but it will be crash when i do memory test size large than 1800M.
    =============================================================
    root@dra7xx-evm:~# free
                     total        used       free         hared      buff/cache      available
    Mem:   3104784     23420   2984596      9716          96768          3038336
    Swap: 0 0 0
    root@dra7xx-evm:~# memtester 2500M 1
    memtester version 4.3.0 (32-bit)
    Copyright (C) 2001-2012 Charles Cazabon.
    Licensed under the GNU General Public License version 2 (only).

    pagesize is 4096
    pagesizemask is 0xfffff000
    want 2500MB (2621440000 bytes)
    got 2500MB (2621440000 bytes), trying mlock ...[ 36.607089] Process 787(false) has RLIMIT_CORE set to 1
    [ 36.612348] Aborting core
    [ 36.615795] BUG: Bad rss-counter state mm:edf30c40 idx:0 val:98
    [ 36.621794] BUG: Bad rss-counter state mm:edf30c40 idx:1 val:7
    [ 37.104010] request_module: runaway loop modprobe binfmt-0000
    [ 37.120341] request_module: runaway loop modprobe binfmt-0000
    [ 37.128183] Core dump to |/bin/false pipe failed
    [ 37.137406] request_module: runaway loop modprobe binfmt-0000
    [ 37.144546] BUG: Bad rss-counter state mm:ee851180 idx:0 val:144
    [ 37.150677] BUG: Bad rss-counter state mm:ee851180 idx:1 val:15
    [ 37.157037] Core dump to |/bin/false pipe failed
    [ 37.164678] BUG: Bad rss-counter state mm:ee850700 idx:0 val:367
    [ 37.170786] BUG: Bad rss-counter state mm:ee850700 idx:1 val:163
    [ 37.178293] BUG: Bad rss-counter state mm:ee851a40 idx:0 val:294
    [ 37.178908] BUG: Bad rss-counter state mm:ee7d5500 idx:0 val:155
    [ 37.178911] BUG: Bad rss-counter state mm:ee7d5500 idx:1 val:19
    [ 37.196421] BUG: Bad rss-counter state mm:ee851a40 idx:1 val:52
    [ 37.202842] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
    [ 37.202842]
    [ 37.212021] CPU1: stopping
    [ 37.214748] CPU: 1 PID: 785 Comm: memtester Tainted: G O 4.4.45-g29f1bae-dirty #314
    [ 37.223570] Hardware name: Generic DRA74X (Flattened Device Tree)
    [ 37.229689] Backtrace:
    [ 37.232167] [<c00130f8>] (dump_backtrace) from [<c00132f4>] (show_stack+0x18/0x1c)
    [ 37.239768] r7:ee5a5df8 r6:20000193 r5:00000000 r4:c0970f8c
    [ 37.245493] [<c00132dc>] (show_stack) from [<c02b496c>] (dump_stack+0x8c/0xa0)
    [ 37.252752] [<c02b48e0>] (dump_stack) from [<c0016420>] (handle_IPI+0x184/0x198)
    [ 37.260177] r7:ee5a5df8 r6:00000000 r5:00000001 r4:c0941424
    [ 37.265896] [<c001629c>] (handle_IPI) from [<c00094c4>] (gic_handle_irq+0x78/0x7c)
    [ 37.273494] r7:fa212000 r6:ee5a5df8 r5:fa21200c r4:c09468dc
    [ 37.279215] [<c000944c>] (gic_handle_irq) from [<c0013dc0>] (__irq_svc+0x40/0x74)
    [ 37.286730] Exception stack(0xee5a5df8 to 0xee5a5e40)
    [ 37.291802] 5de0: ee7d41f8 ecc3c168
    [ 37.300015] 5e00: 00000000 00009b03 edd4ade0 a330c000 00001053 c09ce880 c0949744 ecc3c168
    [ 37.308229] 5e20: ffeee860 ee5a5e54 ee5a5e58 ee5a5e48 c00f3610 c06827e8 60000113 ffffffff
    [ 37.316439] r9:ecc3c168 r8:c0949744 r7:ee5a5e2c r6:ffffffff r5:60000113 r4:c06827e8
    [ 37.324264] [<c06827c4>] (_raw_spin_unlock) from [<c00f3610>] (follow_page_mask+0x314/0x4dc)
    [ 37.332740] [<c00f32fc>] (follow_page_mask) from [<c00f3890>] (__get_user_pages+0xb8/0x57c)
    [ 37.341123] r10:000888e9 r9:ee616600 r8:00001053 r7:ee5a4000 r6:ffffe000 r5:a330c000
    [ 37.349028] r4:edd4ade0
    [ 37.351582] [<c00f37d8>] (__get_user_pages) from [<c00f4264>] (populate_vma_page_range+0x78/0x80)
    [ 37.360488] r10:00000001 r9:ee7d41fc r8:ee7d41c0 r7:b6e23000 r6:00001042 r5:ee5a5f3c
    [ 37.368393] r4:00000000
    [ 37.370946] [<c00f41ec>] (populate_vma_page_range) from [<c00f4310>] (__mm_populate+0xa4/0x140)
    [ 37.379678] r6:edd4ade0 r5:b6e23000 r4:1aa23000
    [ 37.384347] [<c00f426c>] (__mm_populate) from [<c00fb110>] (do_mlock+0x120/0x158)
    [ 37.391859] r10:00000000 r9:00010000 r8:ffffe000 r7:00002000 r6:00000000 r5:1aa23000
    [ 37.399763] r4:9c400000
    [ 37.402316] [<c00faff0>] (do_mlock) from [<c00fb280>] (SyS_mlock+0x14/0x18)
    [ 37.409306] r9:ee5a4000 r8:c000fbc4 r7:00000096 r6:1aa22008 r5:b6f274d0 r4:9c400000
    [ 37.417128] [<c00fb26c>] (SyS_mlock) from [<c000fa20>] (ret_fast_syscall+0x0/0x34)
    [ 37.424737] ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
    [ 37.424737]
    ====================================================================

    Note: Linux kernel config - CONFIG_ARM_LPAE and CONFIG_IOMMU_IO_PGTABLE_LPAE is enable.

  • Hi,
    How is the memory connected to physically to the EMIFs?
    We should make even connection to interleave the EMIF - in this case every EMIF should have (1GB + 512 MB) connected to it.
    Can you please make sure the same? Do you see any problem with that connection?

    Regards,
    Somnath
  • Hi,
    If you have been able to make progress and fix this issue, ,we would like to know about that.

    Regards,
    Somnath
  • This board DDR layout is customer design.
    I have the same qustion as u.The EMIF-1 and EMIF-2 shall be have same DDR unit size.

    Facts of EMIF situation is

    EMIF - 1 : MT41K512M16HA x 2 ( 512M x 16 x 2)
    EMIF - 2 : MT41K256M16TW x 2( 256M x 16 x 2)

  • Hi,
    Given this EMIF connection, you can have first 2GBytes of DDR3 interleaved on EMIF 1 & 2.

    EMIF1 - 1GB (interleaved with EMIF2) + 1GB (non-interleaved)
    EMIF2 - 1GB (interleaved with EMIF1) + "Nothing here"

    You need to configure the LISA registers accordingly.
    Does that make sense?

    Regards,
    Somnath
  • Hi Somnath,

    I already configure LISA registers at evm.c as below

    .dmm_lisa_map_0 = 0x00000000,

    .dmm_lisa_map_1 = 0x00000000,

    .dmm_lisa_map_2 = 0x80740300,

    .dmm_lisa_map_3 = 0xFF020100,

    .is_ma_present = 0x1

    How can i let system know memory mapping is 2G size from 0x80000000, 1G size from 0x100000000? May i descript in kernel command like this =>

    4857.uenv.txt
    args_mmc=part uuid mmc 0:2 uuid; setenv bootargs "console=ttyO3,115200n8 elevator=noop root=PARTUUID=${uuid} rw rootwait earlyprintk fixrtc omapdrm.num_crtc=2 consoleblank=0 cma=64M rootfstype=ext4 snd.slots_reserved=1,1"; mem=2G@0x80000000 mem=1G@0x200000000
       

    Regards,

    Shawn

  • Can anyone help to answer my question?

    Regards,
    Shawn
  • Hi,
    I don't have a direct answer to your question. But I can refer to some code and documentation that should help you derive your configuration. I hope it helps. Please feel free to get back if it doesn't.

    Please take a look at ./board/ti/dra7xx/evm.c
    Refer the LISA structure for 1.5GByte memory:

    static const struct dmm_lisa_map_regs lisa_map_dra7_1536MB = {
    .dmm_lisa_map_0 = 0x0,
    .dmm_lisa_map_1 = 0x80640300,
    .dmm_lisa_map_2 = 0xC0500220,
    .dmm_lisa_map_3 = 0xFF020100,
    .is_ma_present = 0x1
    };

    The above structure defines 2x512 MBytes of memory interleaved on EMIF1 and EMIF2.
    And then there's another 512 MBytes of memory on EMIF2, which is not interleaved.

    Please refer sections like below in the www.ti.com/.../sprui30e.pdf

    15.2.3.5.1.1 Dynamic Mapping
    15.2.3.5.1.2 Address Mapping
    15.2.4.2 Addressing Management with LISA


    Following is the description of the LISA register setting of the above memory configuration.

    .dmm_lisa_map_1 => 0x80640300 => 1000 0000 0110 0100 0000 0011 0000 0000b

    SYS_ADDR[31:24] => 1000 0000 => 80 => DMM system section address MSB for view mapping (i)
    RESERVED[23] => 0 => 0
    SYS_SIZE[22:20] => 110 => 6 => 1 GiB section
    SDRC_CNTL[19:18] => 01 => 1 => 128 byte interleaving
    SDRC_ADDRSPC[17:16] => 00 => 0 => SDRAM controller address space for view mapping (i)
    RESERVED[15:10] => 0000 00 => 0
    SDRC_MAP[9:8] => 11 => 3 => Mapped on EMIF 1 and 2 - interleaved
    SDRC_ADDR[7:0] => 0000 0000 => 00 => SDRAM controller address MSB for view mapping (i)

    .dmm_lisa_map_2 => 0xC0500220 => 1100 0000 0101 0000 0000 0010 0010 0000b

    SYS_ADDR[31:24] => 1100 0000 => C0 => DMM system section address MSB for view mapping (i)
    RESERVED[23] => 0 => 0
    SYS_SIZE[22:20] => 101 => 5 => 512 MiB section
    SDRC_CNTL[19:18] => 00 => 0 => No interleaving
    SDRC_ADDRSPC[17:16] => 00 => 0 => SDRAM controller address space for view mapping (i)
    RESERVED[15:10] => 0000 00 => 0
    SDRC_MAP[9:8] => 10 => 2 => Mapped on EMIF2 only (not interleaved)
    SDRC_ADDR[7:0] => 0010 0000 => 20 => SDRAM controller address MSB for view mapping (i)

    What i can say for you, is that you need to define two LISA sections
    (1) with 2x1 GBytes interleaved on both EMIFs
    (2) 1x1 GBytes non-interleaved on EMIF2.

    Does this help?
    Please feel free to get back on this.

    Regards,
    Somnath
  • Hi Shawn,

    The max configurable size in the DMM is 2GB. Only the MPU can access more than 2GB of memory, and the extended memory map for the MPU is fixed (i.e, not configurable from the LISA registers).

    Since you have 3GB available, I would suggest interleaving 1 GB from both EMIF1 and EMIF2 in the memory range 0x80000000 - 0xFFFFFFFF. You could then access the second 1GB of EMIF1 at address 0x200000000 - 0x23FFFFFFF (after enabling the LPAE feature of the MPU).

    Thus for the LISA register settings, you should set them to the following settings. (This interleaves 1GB from both EMIF1 and EMIF2 in the memory range 0x80000000 - 0xFFFFFFFF).

    static const struct dmm_lisa_map_regs lisa_map_dra7_3GB = {   
        .dmm_lisa_map_0 = 0x00000000,   
        .dmm_lisa_map_1 = 0x00000000,   
        .dmm_lisa_map_2 = 0x80740300,   
        .dmm_lisa_map_3 = 0xFF020100,   
        .is_ma_present = 0x1   
    };

    The extended memory at 0x200000000 won't be accessible by the MPU until LPAE is enabled. Can you elaborate on what software platform you are using?

    Thanks,
    Kevin

  • Hi Shawn,

    As a follow-up, I missed your response showing that you are using the same DMM settings in my previous response.

    If you are using u-boot, please check the function "dram_init_banksize" inside "/board/ti/dra7xx/evm.c", which declares the extended memory sections. You should set the following:

    gd->bd->bi_dram[1].start = 0x200000000;
    gd->bd->bi_dram[1].size = 0x40000000;

    You also need to turn off the high memory interleaving, which is being enabled in u-boot. To do this, comment out the following line of code inside "/arch/arm/cpu/armv7/omap-common/emif-common.c"

    setbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK);

    If you are using different software or the above steps do not fix the issue, please let us know.

    Thanks,
    Kevin

  • Hi Kevin,

    Thanks a lot, this indeed solve my problem.

    Regards,
    Shawn