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DRA72XEVM: DRA7xx GPIO Access

Part Number: DRA72XEVM

Hi,

I am having Jacinto J6 EVM ( spectrumdigital.com/jacinto-6-infotainment-evaluation-module-kit )

I can see a bunch of gpio files in /sys/class/gpio (gpio0,gpio128,gpio160,gpio192,gpio224 etc).

Where is the hardware pin for these GPIO's which has sys interface. Is it in COM8 Connector or is it in the connector of Vision Application board?

Is it enabled by default on Processor SDK.

  • Hi Ganesh,

    The sysfs list you see is representing all 8 GPIO banks present in dra7x devices (each bank 32 pins each), this sysfs interface is enabled via CONFIG_GPIO_SYSFS kernel config.

    Link below explains how to use the sysfs interface to dynamically configure a GPIO through sysfs.
    https://www.kernel.org/doc/Documentation/gpio/sysfs.txt


    To understand which H/W GPIO pins are used,
    - Browse through the TI EVM dts files, or
    - Look at /sys/kernel/debug/gpio debugfs entry.


    Regards,
    Vishal

  • Hi Vishal,

    In Interface Connection EXP_P1 i can see GP5[29],GP5[30],GP5[31] .
    How am i supposed to calculate the bank and export the gpio pin number.
    I saw two methods when i googled, which one is applicable for DRA7x
    gpionumber = ((gpiobank-1)*ngpio)+gpiobit
    ((5-1)*32)+29 = 157

    and next method is
    all gpio controllers have label gpio

    so if i calculate from starting

    /sys/class/gpio/gpiochip0 gpio 0 32 - Bank 1
    /sys/class/gpio/gpiochip128 gpio 128 32 - Bank 2
    /sys/class/gpio/gpiochip160 gpio 160 32 - Bank 3
    /sys/class/gpio/gpiochip192 gpio 192 32 - Bank 4
    /sys/class/gpio/gpiochip224 gpio 224 32 - Bank 5

    gpionumber = gpiobase + our GPIO of interest in block D
    224+29= 253

    which one is correct?

  • Hi Ganesh,

    You should see more folders in /sys/class/gpio, each gpiochip<x> folder represents a GPIO bank.

    shell@jacinto6evm:/ # ls -l /sys/class/gpio/
    --w------- root root 4096 2000-01-01 00:02 export
    lrwxrwxrwx root root 2000-01-01 00:02 gpiochip0 -> ../../devices/virtual/gpio/gpiochip0
    lrwxrwxrwx root root 2000-01-01 00:02 gpiochip128 -> ../../devices/virtual/gpio/gpiochip128
    lrwxrwxrwx root root 2000-01-01 00:02 gpiochip160 -> ../../devices/virtual/gpio/gpiochip160
    lrwxrwxrwx root root 2000-01-01 00:02 gpiochip192 -> ../../devices/virtual/gpio/gpiochip192
    lrwxrwxrwx root root 2000-01-01 00:02 gpiochip224 -> ../../devices/virtual/gpio/gpiochip224
    lrwxrwxrwx root root 2000-01-01 00:02 gpiochip32 -> ../../devices/virtual/gpio/gpiochip32
    lrwxrwxrwx root root 2000-01-01 00:02 gpiochip432 -> ../../devices/44000000.ocp/4807a000.i2c/i2c-3/3-0021/gpio/gpiochip432
    lrwxrwxrwx root root 2000-01-01 00:02 gpiochip448 -> ../../devices/44000000.ocp/48072000.i2c/i2c-1/1-0026/gpio/gpiochip448
    lrwxrwxrwx root root 2000-01-01 00:02 gpiochip464 -> ../../devices/44000000.ocp/48070000.i2c/i2c-0/0-0021/gpio/gpiochip464
    lrwxrwxrwx root root 2000-01-01 00:02 gpiochip480 -> ../../devices/44000000.ocp/48070000.i2c/i2c-0/0-0027/gpio/gpiochip480
    lrwxrwxrwx root root 2000-01-01 00:02 gpiochip496 -> ../../devices/44000000.ocp/48070000.i2c/i2c-0/0-0020/gpio/gpiochip496
    lrwxrwxrwx root root 2000-01-01 00:02 gpiochip64 -> ../../devices/virtual/gpio/gpiochip64
    lrwxrwxrwx root root 2000-01-01 00:02 gpiochip96 -> ../../devices/virtual/gpio/gpiochip96
    --w------- root root 4096 2000-01-01 00:02 unexport



    The folders gpiochip0 through gpiochip224 represents GPIO bank 1 through 8.

    The EVM also has PCF GPIO expanders for additional pins (http://www.ti.com/product/PCF8575)
    gpiochip432 to gpiochip496 represents these PCF expanders on the board.


    --------------------

    Your initial calculation looks correct

    gpionumber = ((gpiobank-1)*ngpio)+gpiobit
    ((5-1)*32)+29 = 157

  • Hi Vishal,

    But if i export 157 i am not getting a folder corresponding to 157 in /sys/class/gpio.
    echo 157 > /sys/class/gpio/export
  • - Do you see all the GPIO banks like what I showed in previous reply?
    - Do you see any error messages on the console when you try to export?
    - What SDK version are you using?

  • Hi Vishal,

    Yes i see all banks as mentioned in previous post. No error message was thrown when i tried to export. But the folder corresponding to the gpio was not created and there was no messages in dmesg.
  • I just tried it on TI EVM and I see it working,

    jacinto6evm:/sys/class/gpio # ls
    export gpiochip160 gpiochip32 gpiochip478 gpiochip64
    gpiochip0 gpiochip192 gpiochip446 gpiochip494 gpiochip96
    gpiochip128 gpiochip224 gpiochip462 gpiochip510 unexport

    jacinto6evm:/sys/class/gpio # echo 157 > /sys/class/gpio/export


    jacinto6evm:/sys/class/gpio # ls

    export gpiochip128 gpiochip224 gpiochip462 gpiochip510 unexport
    gpio157 gpiochip160 gpiochip32 gpiochip478 gpiochip64
    gpiochip0 gpiochip192 gpiochip446 gpiochip494 gpiochip96


  • Hi Vishal,

    Now its exporting and i am getting the folder. But the pin is not turning high, when i am setting it using echo 1 > /sys/class/gpio157/value

    Schematic of EXP_P1

    pasteboard.co/HtV3tLz.png

    i am taking GP5[29],GP5[30],GP5[31], But the GPIO is connected to a switch, which by default enables ethernet and GPIO will be disabled

    Schematic of switch

    pasteboard.co/HtV4Ncj.png

    Is it possible to toggle SEL_ENET_MUX_S0 from software? How can i change SEL_ENET_MUX_S0 so that Ethernet is disabled and GPIO is enabled?

  • Hi,

    Try adding below lines to pcf_gpio_21 node in dra7-evm.dts to configure SEL_ENET_MUX_S0.
    Use property output-low to drive this pin low and output-high to drive the pin high

    diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
    index 25070a073a94..93474cb34b13 100644
    --- a/arch/arm/boot/dts/dra7-evm.dts
    +++ b/arch/arm/boot/dts/dra7-evm.dts
    @@ -806,6 +806,13 @@
                    interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
                    interrupt-controller;
                    #interrupt-cells = <2>;
    +               enet_brdmux: p4 {
    +                       /* sel_enet_mux_s0 */
    +                       gpio-hog;
    +                       gpios = <4 GPIO_ACTIVE_HIGH>;
    +                       output-low;
    +                       line-name = "sel_enet_mux_s0";
    +               };
            };
    
            tlv320aic3106: tlv320aic3106@19 {
    




    Regards,
    Vishal

  • Hi Vishal,

    I edited the dts files compiled the kernel again and copied the dtb's and zImage to boot folder in rootfs.
    Then i tried making the gpio pins high but there was no change. The one change i saw was the LCD touch display was not up even i selected lcd-osd dtb in uenv.txt . Both the ethernet port was not up. This is the message i got in dmesg

    leds backlight: Failed setting brightness
    [ 8.076821] net eth1: initializing cpsw version 1.15 (0)
    [ 8.100236] net eth0: initialized cpsw ale version 1.4
    [ 8.122340] net eth0: ALE Table size 1024
    [ 8.141955] libphy: PHY 48485000.mdio:03 not found
    [ 8.156652] net eth1: phy "48485000.mdio:03" not found on slave 1, err -19
    [ 8.185672] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready
    [ 8.220130] net eth0: initializing cpsw version 1.15 (0)
    [ 8.245887] libphy: PHY 48485000.mdio:02 not found
    [ 8.260632] net eth0: phy "48485000.mdio:02" not found on slave 0, err -19
    [ 8.294112] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
  • Did you add it in the right place?
    The change should go to dts node labelled "pcf_gpio_21: gpio@21"

  • Hi Vishal,

    Yes it was pasted under the node labelled 21

    pcf_lcd: gpio@20 {
    compatible = "nxp,pcf8575";
    reg = <0x20>;
    gpio-controller;
    #gpio-cells = <2>;
    interrupt-parent = <&gpio6>;
    interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
    interrupt-controller;
    #interrupt-cells = <2>;
    };
    
    pcf_gpio_21: gpio@21 {
    compatible = "ti,pcf8575";
    reg = <0x21>;
    lines-initial-states = <0x1408>;
    gpio-controller;
    #gpio-cells = <2>;
    interrupt-parent = <&gpio6>;
    interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
    interrupt-controller;
    #interrupt-cells = <2>;
    enet_brdmux: p4 {
    gpio-hog;
    gpios = <4 GPIO_ACTIVE_HIGH>;
    output-low;
    line-name = "sel_enet_mux_s0";
    };
    };
    
    tlv320aic3106: tlv320aic3106@19 {
    #sound-dai-cells = <0>;
    compatible = "ti,tlv320aic3106";
    reg = <0x19>;
    adc-settle-ms = <40>;
    ai3x-micbias-vg = <1>; /* 2.0V */

  • Hi,

    This change should not have affected LCD. But Ethernet could be affected based on how the lines are muxed between ports
    https://pasteboard.co/HtV4Ncj.png


    1) What happens when you change from "output-low" to "output-high" in the gpio hog settings of dts?


    2) Also, make sure you add entries in u-boot pin mux settings for GPIO5 pins you want to use.

        File: board/ti/dra7xx/mux_data.h
        Structure: dra74x_core_padconf_array

    diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
    index d0cc4b68b5..0dd74e88fc 100644
    --- a/board/ti/dra7xx/mux_data.h
    +++ b/board/ti/dra7xx/mux_data.h
    @@ -790,9 +790,9 @@ const struct pad_conf_entry dra74x_core_padconf_array[] = {
            {RGMII0_RXC, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},  /* rgmii0_rxc.rgmii0_rxc */
            {RGMII0_RXCTL, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)},        /* rgmii0_rxctl.rgmii0_rxctl */
            {RGMII0_RXD3, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd3.rgmii0_rxd3 */
    -       {RGMII0_RXD2, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd2.rgmii0_rxd2 */
    -       {RGMII0_RXD1, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd1.rgmii0_rxd1 */
    -       {RGMII0_RXD0, (M0 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* rgmii0_rxd0.rgmii0_rxd0 */
    +       {RGMII0_RXD2, (M14 | PIN_INPUT_PULLDOWN)},      /* rgmii0_rxd2.gpio5_29 */
    +       {RGMII0_RXD1, (M14 | PIN_INPUT_PULLDOWN)},      /* rgmii0_rxd1.gpio5_30 */
    +       {RGMII0_RXD0, (M14 | PIN_INPUT_PULLDOWN)},      /* rgmii0_rxd0.gpio5_31 */
            {USB1_DRVVBUS, (M0 | PIN_INPUT_SLEW)},  /* usb1_drvvbus.usb1_drvvbus */
            {USB2_DRVVBUS, (M0 | PIN_INPUT_SLEW)},  /* usb2_drvvbus.usb2_drvvbus */
            {GPIO6_14, (M9 | PIN_INPUT_PULLUP)},    /* gpio6_14.i2c3_sda */
    

    Regards,
    Vishal

  • Hi Ganesh,

    Ignore the point #1 from previous comment. It should be output-low. The observation that Ethernet stopped working could mean that the mux is now choosing other set of pins and the gpio-hog change is taking effect. (RGMII pins are for Ethernet)

    Make sure you have the pinmux configured in the u-boot for choosing GPIO5 pins over RGMII

    Regards,
    Vishal
  • Hi Vishal,

    When did the above mentioned changes in uboot , all three gpio worked, but the problem is i lost both the ethernet port and LCD display is also not working. I thought i will be losing one ethernet port for gpio. How can i make the other ethernet port working along with LCD?

    dmesg output

    ] net eth1: initializing cpsw version 1.15 (0)
    [ 7.127790] net eth0: initialized cpsw ale version 1.4
    [ 7.153977] net eth0: ALE Table size 1024
    [ 7.187532] libphy: PHY 48485000.mdio:03 not found
    [ 7.208932] net eth1: phy "48485000.mdio:03" not found on slave 1, err -19
    [ 7.267904] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready
    [ 7.300497] net eth0: initializing cpsw version 1.15 (0)
    [ 7.336740] libphy: PHY 48485000.mdio:02 not found
    [ 7.362943] net eth0: phy "48485000.mdio:02" not found on slave 0, err -19
    [ 7.417511] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
    [ 7.698128] random: nonblocking pool is initialized
    [ 8.469162] leds backlight: Failed setting brightness
  • Can you share the u-boot/kernel changes you have done so far?
  • Hi Ganesh,

    I tried the pcf pin4 change on Rev-H EVM here and I don't see an issue with LCD panel. 
    https://e2e.ti.com/support/arm/automotive_processors/f/1020/p/701154/2608561#2608561

    I do see the same behavior on Ethernet, I will get back to you on the Ethernet behavior.
    But I don't see any issue with LCD display with this change.

    Regards,
    Vishal

  • Hi Ganesh,

    None of the Ethernet port will work with the change to SEL_ENET_MUX_S0 for selecting GPIO5 pins.
    Changes to SEL_ENET_MUX_S0 also changes SEL_ENET_MUX_S1.

    SEL_ENET_MUX_S1 controls the MDIO pins and MDIO pins are needed for any Ethernet port to work.








  • Hi Vishal,


    Do we have any workaround for this or do i have to choose another set of GPIO. In EXP_P2 i can see three GPIO's should i choose those, will it bring any conflict with other peripherals.

  • Hi Ganesh,

    You have to look at schematics and figure out which pins would work for your use case.

    Regards,
    Vishal
  • Hi Vishal,

    As per schematics the three pins GP5[0], GP5[1] & GP5[17] is connected to EXP_P2. These three pins are connected directly to SoC, so do we need to do any Mux changes or can we directly export it as gpio and start using it.

    Schematic of EXP_P2 with GPIO's highlighted

    pasteboard.co/HvUlrR4.png

    Schematics of GPIO's connection to soc

    pasteboard.co/HvWybJT.png

    pasteboard.co/HvWyhVG.png
  • GP5[0] and GP5[1] have no conflict, You just have to update corresponding pinmux in boot loader for choosing these GPIO pins over mcasp1_aclkr and mcasp1_fsr pins. Similar to changes shown earlier - https://e2e.ti.com/support/arm/automotive_processors/f/1020/p/701154/2618639#2618639 
    But, in this case you have to add new entries for these pins.

    GP5[17], I am not sure, this pin conflicts with RMII_MHZ_50_CLK, which could have impact on Ethernet.
    You could try changing pinmux of RMII_MHZ_50_CLK to gpio5_17 and check if Ethernet is still functional.


    Code snippet below shows the modifications to be done in u-boot, update the input/output/pull settings of the pins based on your usage. 

    diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
    index d0cc4b68b5..b1ff60175d 100644
    --- a/board/ti/dra7xx/mux_data.h
    +++ b/board/ti/dra7xx/mux_data.h
    @@ -852,6 +852,9 @@ const struct pad_conf_entry dra74x_core_padconf_array[] = {
            {I2C2_SCL, (M0 | PIN_INPUT_PULLUP)},    /* i2c2_scl.i2c2_scl */
            {WAKEUP0, (M15 | PULL_UP)},     /* Wakeup0.safe for dcan1_rx */
            {WAKEUP2, (M14)},               /* Wakeup2.gpio1_2 */
    +       {RMII_MHZ_50_CLK, (M14 | PIN_INPUT_PULLUP)},    /* RMII_MHZ_50_CLK.gpio5_17 */
    +       {MCASP1_ACLKR, (M14 | PIN_INPUT)},      /* mcasp1_aclkr.gpio5_0 */
    +       {MCASP1_FSR, (M14 | PIN_INPUT)},        /* mcasp1_fsr.gpio5_1 */
    
     #ifdef CONFIG_DRA7XX_JAMR3
            {XREF_CLK1, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk1.atl_clk1 */

  • Hi Vishal,

    Do we need any changes in dts file along with uboot changes?

  • No change needed in dts.
  • Hi Vishal,

    As per our previous calculation i got gpio pin values as GP5[0]=128,GP5[1]=129 and GP5[17]=145. All of these pins can be exported as gpio and is listing.
    For GP5[0], i am able to configure it as input and is giving high and low correctly on value variable when provided the same.
    For GP[17], the default state of the pin is high, even if it is not connected to 3.3 the pin is showing high and in multimeter its 3.3, if i ground the pin it becomes zero. why is it in high state even if it is not connected to vcc?
    For GP5[1], this pin is configured as input, No change is reflecting on this pin. Its giving low on value variable even i connect it to 3.3?
  • I have to check with H/W team on GP5[17] behavior and get back.

    Could you try adding PULLUP or PULLDOWN settings in the pinmux settings (u-boot pinmux changes) for these pins and see if there is any difference in behavior?
  • Hi Vishal,

    GP5[17] is working fine when i converted pinmux to {RMII_MHZ_50_CLK, (M14 | PIN_INPUT)},

    But the issue with GP5[1] still persists if the mux configuration is MCASP1_FSR, (M14 | PIN_INPUT)} the value will be always zero. If i connect the pin to 3.3v, still the value variable gives zero.

    If i change {MCASP1_FSR, (M14 | PIN_INPUT_PULLUP)}, the value variable always gives one even if connect it to the ground.

    What could be the reason? How can i fix it? Does this require any changes in dts?
  • What is the behavior, if you change GP5[1] configuration to PULLDOWN?
  • Hi Ganesh,

    Do you need any more help with this topic?

    Regards,
    Vishal
  • Hi Vishal,

    Even if i pulldown the value will be always zero. If i connect the pin to 3.3v, still the value variable gives zero.
  • Hi Ganesh,

    Your initial query about GPIO access is answered.
    Please open a new question for GP5[1] behavior.

    Regards,
    Vishal