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Linux/DRA718: booting fail.

Part Number: DRA718
Other Parts Discussed in Thread: LP8732-Q1, LP8733-Q1

Tool/software: Linux

Dear,

J6 Entry DRA718 1004.nu100_20180419-core-TI.pdfcan't boot from SD card (QSPI and eMMC are both empty), there isn't any message on UART1 TX.

My condition is

a. Power up sequence as LP8733-Q1 and LP8732-Q1 User’s Guide to Power J6Entry Figure 2. 

b. booting loader (518202 J6 entry EVM board version) in SD card.

c. choice SYSBOOT[5:0]= 0b100010 => SD boot.

d. Use 19.2MHz crystal on J6 Entry and sysboot[9:8] = 0b11 (19.2MHz is 518392 J6 ENTRY LOW REF version ).

e. reset signal (porz) is high.

We try to change booting loader to 518392 J6 ENTRY LOW REF version(download from web), but it still without any message on UART. 

(Maybe the download 518392 loader isn't correct.)

Could you advise me what to do?

Thanks a lot.

Ryan.

  • Hi Ryan,

    Could you please add details about the location from where you downloaded the 518392 loader? It is not very clear at the moment.

    Regards
    Karthik
  • Hello, Karthik,

    I download the uboot from

    www.ti.com/.../TIDEP-0097 ==>

    User guides (Cost-Effective In-Vehicle Infotainment System Reference Design)

    www.ti.com/.../tidudn2.pdf ==> Page 11 , uboot

    Thanks.

    Ryan.

  • Hi Ryan,
    Can you tell us what do you refer here by 518202 or 518392? What do these numbers refer?
    Can you paste the link from where you downloaded the software? Are you trying to boot Android on the EVM?

    Regards,
    Somnath
  • Hello, Somnath,

    Sorry, I didn't make it very clear.

    518202 is Spectrum Digital EVM (DRA71x/DRA79x/TDA2Ex-17/AM570x CPU Board Kit) schematic document number.

    518392 is TI J6 ENTRY LOW REF EVM board schematic document number.

    I downloaded software from omappedia.org/.../6AM.1.3_Release_Notes.

    Thanks a lot.

    Ryan.

  • Hi,
    Thanks for letting us know about the detail.
    Are you trying to rebuild the U-boot or kernel?
    Are you trying to run this on the EVM itself? Has the EVM undergone any modification?

    Regards,
    Somnath
  • Hi Ryan,

    The reference software provided for 518392 board does not support SD card boot.
    Please follow the instructions in section 3.1.3 of the document for flashing the board using USB peripheral boot.

    http://www.ti.com/lit/ug/tidudn2/tidudn2.pdf

    Regards,
    Vishal

  • Hi, Somnath,

     Yes, we rebuild U-boot and run on Spectrum Digital EVM ,

    but it still can't run on our PCBA.

    We don't do any modification on Spectrum Digital EVM board.

    Thanks.

    Ryan.

  • Hi, Vishal,

    Since our PCBA don't have USB , so it hard to use 518392 reference software.

    Now we use Spectrum Digital EVM U-boot version, and try to use 19.2MHz setting.

    This U-boot can run on Spectrum Digital EVM, but can't run on our PCBA.

    Thanks.

    Ryan.
  • Hi Ryan,

    Is your PCBA similar to 518202 or 518392?
    You should use u-boot from one of our Android or Linux SDK releases.

    Regards,
    Vishal
  • Hello, Vishal

    Our PCBA is similar 518202 (Spectrum Digital EVM ) besides DDR3L.

    We use two 16bits DDR3L as 518392 (TI J6 ENTRY LOW REF EVM board ).

    So we use Spectrum Digital EVM u-boot of Linux SDK.

    Thanks.

    Ryan.
  • Hi,

     I measured  DDR3L  CKE and CLK_P signal on our board and Spectrum Digital EVM board (as attached file).

    It looks like DDR3L doesn't work on our board, but I don't know why?

    I already changed our board J6 Entry Crystal to 20MHz and set SYSboot to 20MHz.

    I even try to boot from QSPI (burn on Spectrum Digital EVM board and rebuild to our board) , but it still booting fail.

    Could anybody give me any suggestion?

    Thanks a lot.

    Ryan.

  • Hi, 

    I used  XDS100v2 JTAG Debug Probe to connect our target board,

    the CCS message are below.

    What may cause PRCM Configuration timeout?

    Cortex_M4_IPU1_C0: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence In Progress... <<<---

    Cortex_M4_IPU1_C0: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence DONE! <<<---

    Cortex_M4_IPU1_C1: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence In Progress... <<<---

    Cortex_M4_IPU1_C1: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence DONE! <<<---

    Cortex_M4_IPU2_C0: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence In Progress... <<<---

    Cortex_M4_IPU2_C0: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence DONE! <<<---

    Cortex_M4_IPU2_C1: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence In Progress... <<<---

    Cortex_M4_IPU2_C1: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence DONE! <<<---

    C66xx_DSP1: GEL Output: --->>> DRA72x C66x DSP Startup Sequence In Progress... <<<---

    C66xx_DSP1: GEL Output: --->>> DRA72x C66x DSP Startup Sequence DONE! <<<---

    CortexA15_0: GEL Output: --->>> DRA72x Cortex A15 Startup Sequence In Progress... <<<---

    CortexA15_0: GEL Output: --->>> DRA72x Cortex A15 Startup Sequence DONE! <<<---

    IcePick_D: GEL Output: Ipu RTOS is released from Wait-In-Reset.

    IcePick_D: GEL Output: Ipu SIMCOP is released from Wait-In-Reset.

    IcePick_D: GEL Output: IVAHD C66 is released from Wait-In-Reset.

    IcePick_D: GEL Output: IVAHD ICONT1 is released from Wait-In-Reset.

    IcePick_D: GEL Output: IVAHD ICONT2 is released from Wait-In-Reset.

    CS_DAP_DebugSS: GEL Output: --->>> CONFIGURE DEBUG DPLL settings to 1.9 GHZs <<<---

    CS_DAP_DebugSS: GEL Output: > Setup DebugSS 1.9GHz in progress...

    CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz

    CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS PLL Clocking 1.9GHz

    CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS ATB Clocking 380MHz

    CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz

    CS_DAP_DebugSS: GEL Output: --->>> TURNING ON L3_INSTR and L3_3 clocks required for debug instrumention <<<<<<----

    CS_DAP_DebugSS: GEL Output: ---<<< L3 instrumentation clocks are enabled >>>> ---

    CS_DAP_DebugSS: GEL Output: --->>> Mapping TIMER supsend sources to default cores <<<<<<----

    CS_DAP_PC: GEL Output: Cortex-A15 1 is not in WIR mode so nothing to do.

    CortexA15_0: GEL Output: --->>> DRA72x Target Connect Sequence Begins ... <<<---

    CortexA15_0: GEL Output: --->>> DRA72x PG1.0 GP device <<<---

    CortexA15_0: GEL Output: --->>> The core is in non-SECURE state. <<<---

    CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<---

    CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 clock config is in progress...

    CortexA15_0: GEL Output: Cortex A15 DPLL is already locked, now unlocking...

    CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 is DONE!

    CortexA15_0: GEL Output: IVA DPLL OPP 0 clock config is in progress...

    CortexA15_0: GEL Output: IVA DPLL OPP 0 is DONE!

    CortexA15_0: GEL Output: PER DPLL OPP 0 clock config in progress...

    CortexA15_0: GEL Output: PER DPLL already locked, now unlocking

    CortexA15_0: GEL Output: PER DPLL OPP 0 is DONE!

    CortexA15_0: GEL Output: CORE DPLL OPP 0 clock config is in progress...

    CortexA15_0: GEL Output: CORE DPLL OPP already locked, now unlocking....

    CortexA15_0: GEL Output: CORE DPLL OPP 0 is DONE!

    CortexA15_0: GEL Output: ABE DPLL OPP 0 clock config in progress...

    CortexA15_0: GEL Output: ABE DPLL OPP 0 is DONE!

    CortexA15_0: GEL Output: GMAC DPLL OPP 0 clock config is in progress...

    CortexA15_0: GEL Output: GMAC DPLL OPP 0 is DONE!

    CortexA15_0: GEL Output: GPU DPLL OPP 0 clock config is in progress...

    CortexA15_0: GEL Output: GPU DPLL OPP 0 is DONE!

    CortexA15_0: GEL Output: DSP DPLL OPP 0 clock config is in progress...

    CortexA15_0: GEL Output: DSP DPLL OPP 0 is DONE!

    CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 clock config is in progress...

    CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 is DONE!

    CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<---

    CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<---

    CortexA15_0: GEL Output: module_base: 0x4A009700

    CortexA15_0: GEL Output: module_offset: 0x000000C8

    CortexA15_0: GEL Output: TIMEOUT

    CortexA15_0: GEL Output: module_base: 0x4A009700

    CortexA15_0: GEL Output: module_offset: 0x000000D0

    CortexA15_0: GEL Output: TIMEOUT

    CortexA15_0: GEL Output: module_base: 0x4A009700

    CortexA15_0: GEL Output: module_offset: 0x000000D8

    CortexA15_0: GEL Output: TIMEOUT

    CortexA15_0: GEL Output: module_base: 0x4A009700

    CortexA15_0: GEL Output: module_offset: 0x00000130

    CortexA15_0: GEL Output: TIMEOUT

    CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<---

    CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<---

    CortexA15_0: GEL Output: DDR DPLL clock config for 666MHz is in progress...

    CortexA15_0: GEL Output: DDR DPLL clock config for 666MHz is in DONE!

    CortexA15_0: GEL Output: Launch full leveling

    CortexA15_0: GEL Output: Updating slave ratios in PHY_STATUSx registers

    CortexA15_0: GEL Output: as per HW leveling output

    CortexA15_0: GEL Output: HW leveling is now disabled. Using slave ratios from

    CortexA15_0: GEL Output: PHY_STATUSx registers

    CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<---

    CortexA15_0: GEL Output: --->>> DRA72x Target Connect Sequence DONE !!!!! <<<---

     

     

    Thanks a lot.

    Ryan.

  • Hi,
    Do you need any further help on this?
    Can you let us know what help you need or what are you blocked on?

    Regards,
    Somnath
  • Hi, 

    It seems message block on PRCM timer 13~16 and timeout.

    Could you suggest me what may cause PRCM Configuration timeout?

    Thanks a lot.

    Ryan.

  • Hi,
    Can you let me know what further help you need on this?

    Regards,
    Somnath
  • Hi,
    Can you check all your PMIC voltages e.g. VD_CORE and others are in right level?
    These timers are in CD_L4PER3.

    They are failing to wake up - could be because of Voltages are not in right state or the PLL is not locked yet.

    Regards,
    Somnath
  • Hi,
    Do you need any further help on this?

    Regards,
    Somnath
  • Hi, Somnath,

    Thanks your suggestion. The PMIC output level are in right level.
    We found the root cause of timer 13~16 time out is without build OSC1 to DRA718.
    We also found root cause of the system hang on is DDR3L setting parameter.

    Thanks a lot.

    Ryan.
  • Hi,
    Can you share the root cause of both the problems?

    Regards,
    Somnath