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TDA3: DCC Valid0 Value

ROGERG
Mastermind 34680 points

Part Number: TDA3

Dear Experts,

assuming the following configuration:

- Reference Clock = 32kHz ; Test Clock = 20MHz; allowed deviation of Test Clock = 0.02%

I end up with a value of "0" for Valid0 counter. I am wondering about

1) Is it allowed to have a "0" for Valid0 or is at least a "1" value necessary for Valid0 counter in this case?

2) Is there a general limit with regards to the deviation accuracy?

Calculations:

Many thanks and best regards,

Gregor

  • 0
    TI__Expert 4885 points
    Hi, Gregor,

    Please, refer to DCC chapter in the TRM

    There you can find the deviation accuracy and explanation of the meaning of Counter0, Valid0 and counter1.

    I am not an expert on DCC, but I think I can give you more information on the values on e-mail.

    Regards,
    Mariya
  • 0 in reply to Mariya Petkova
    TI__Mastermind 34680 points

    For completeness, I got the following information:

    1) Is it allowed to have a "0" for Valid0 or is at least a "1" value necessary for Valid0 counter in this case? I assume a minimum of 1 for the slower clock needs to be used, could You please confirm?

    Valid0 cannot be programmed as ‘0’. It should be equivalent to 1 clock cycle period(at minimum) of the slower clock in case where there is 0% allowed drift.

    2) Is there a general limit with regards to the deviation accuracy? In the TRM it says: “Specifically, the DCC is expected to detect 2% drift from the expected frequency within 100ms time.”

    Yes, there is in-general limitation on minimum detectable/allowed drift in test clock for a given time period. It is dependent on ratio of these two clock(i.e. Test clock and Reference clock).

    For above case, where Reference clock = 32kHz and Test clock = 20MHz, it not possible to detect a drift of 0.02% using DCC.