TDA3: How to estimate power consumption at the PORz reset

Hi Kenshow,

I have forwarded your question to expert to comment.

Regards,
Yordan

Hi I am curios also about this topic.

From my know how the internal cores are disabled/gated at power up. So normally should not have leakage curent(or very small).
1W@ is the leakage power of the device when it has some if not all cores of TDA3M activated (0%).

Is my assumption wrong?
Thank you.

Hi,

Roughly,

At running state:

Total consumption = Switching consumption + leakage currents

When SoC is at reset, can say almost no clocks are running and no switching consumption. therefore:

Total Consumption = leakage currents

Regards,

Stan

Hurdugaciu-san,

If I look into the TRM, I find that the device is broken into the following power domains (Section 3.4.1). These power domains are controlled through the POWERSTATE bit-field and I scanned the different domains for their default state. What I find is that the ISS, DSP{1 and 2} and EVE domains default to an ON state.  Additionally, the Always ON domains will be in their ON state as well.

Bottom line: Some modules (VIP, IPU, DSS, and EFUSE) are disabled; most modules are powered with slow clocks.

Kevin

Power Domain	Default Power State
PD_WKUPAON
PD_COREAON
PD_CAM	PM_CAM_PWRSTCTRL[1:0].POWERSTATE defaults to 0x00 (OFF)
PD_IPU	PM_IPU_PWRSTCTRL[1:0].POWERSTATE defaults to 0x00 (OFF)
PD_DSS	PM_DSS_PWRSTCTRL[1:0].POWERSTATE defaults to 0x00 (OFF)
PD_CUSTEFUSE	PM_CUSTEFUSE_PWRSTCTRL[1:0].POWERSTATE defaults to 0x00 (OFF)
PD_ISS	PM_ISS_PWRSTCTRL[1:0].POWERSTATE defaults to 0x03 (ON)
PD_DSP1	PM_DSP1_PWRSTCTRL[1:0].POWERSTATE defaults to 0x03 (ON)
PD_DSP2	PM_DSP2_PWRSTCTRL[1:0].POWERSTATE defaults to 0x03 (ON)
PD_EVE	PM_EVE1_PWRSTCTRL[1:0].POWERSTATE defaults to 0x03 (ON)

 
 
 


 
 
  

Hi Kevin,

Thanks for the information, I thought that PD_DSP1,2 AND PD_EVE are off state.
And is strange that PD_IPU is OFF and the one mentioned above are ON.

This explains the high leakage.
So we obtain lower leakage power (beside turning off the external VDD) if we turn on the device and put everything (what is possible) in sleep mode?

I have an additional question related with the PD.
I see in the Table 3-27. PMFW Device-Level Layout :
PD_COREAON
PD_WKUPAON
PD_IPU
PD_CUSTEFUSE
PD_CAM
PD_DSS
PD_ISS
PD_DSP1
PD_DSP2
PD_EVE1
But I see also text about :
PD_CORE
PD_L3INIT
PD_L4PER
PD_EMU
PD_MMAON

How we can control the latest one?

regards,
Mihai H

Hi,

AON = Always-ON

That is,

PD_COREAON
PD_WKUPAON and

PD_MMAON

Cannot be switch off.

Regards,

Stan

Ok , 

and for ?

PD_CORE
PD_L3INIT
PD_L4PER
PD_EMU