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TDA2EVM5777: How to use camera as the input of the TIDL net?

Part Number: TDA2EVM5777

Hi,

I have read the development guide and knows how to generate a normal algorithm program based on the camera input and LCD output. But I am not able to combine the camera input program with the TIDL.

Could you tell me how to write a program that the board can use camera as the TIDL net's input and display the output on the LCD?

I have tried use the below configration file to generate the use-case file. Is it correct?

Thank you.

UseCase: chains_tidlEve

Capture -> Alg_tidlpreproc (A15)
Alg_tidlpreproc (A15) -> Alg_tidl_1 (EVE1)
Alg_tidlpreproc (A15) -> Alg_tidl_2 (EVE2)
Alg_tidl_1 (EVE1) -> Merge (IPU1_0)
Alg_tidl_2 (EVE2) -> Merge (IPU1_0)
Merge (IPU1_0) -> Display_Video
GrpxSrc -> Display_Grpx

  • Sorry. The configration file I used is as the file below. I typed the wrong one.

    UseCase: chains_tidlEve

    Capture -> Alg_tidlpreproc (A15)
    Alg_tidlpreproc (A15) -> Alg_tidl_1 (EVE1)
    Alg_tidlpreproc (A15) -> Alg_tidl_2 (EVE2)
    Alg_tidl_1 (EVE1) -> Merge (IPU1_0)
    Alg_tidl_2 (EVE2) -> Merge (IPU1_0)
    Merge (IPU1_0) -> Display_Video
    GrpxSrc -> Display_Grpx
  • Hi,

    I have forwarded your question to VisionSDK experts.

    Regards,
    Yordan
  • Hi,

    The TIDL algorithm requires BGR planar input which the capture link cannot provide.

    Also the output of the TIDL is segment index value between 0-4 for every pixel.

    regards,

    Anand

  • Thank you, Anand.
    Thus, is there any other solution that the camera can be used as the TIDL input?
    Regards
    Kai
  • Or, is it possible to convert the capture link's output to BGR planar?
    Thank you.

  • Hi,

    No capture link cannot output planar BGR.

    There is tidl pre process alg plug-in which you can modify to convert YUV to planar BGR format with the required padding for tidl algorithm.

    regards,

    Anand

  • Hi Anand, I am the workmate of Kaixiang Ye, I am trying finishing the work. When running on TDA2xx, some errors have occurred, and the log information is here:


    [IPU1-0] Core Menu
    [IPU1-0] ====================
    [IPU1-0]
    [IPU1-0] 1: DSP
    [IPU1-0] 2: EVE
    [IPU1-0]
    [IPU1-0] Enter Choice:
    [IPU1-0]
    [IPU1-0] 257.539834 s:
    [IPU1-0]
    [IPU1-0] ====================
    [IPU1-0] Use case Mode
    [IPU1-0] ====================
    [IPU1-0]
    [IPU1-0] 1: Dump Output Frames to file
    [IPU1-0] 2: Free Run (Output Frames are not dumped)
    [IPU1-0]
    [IPU1-0] Enter Choice:
    [IPU1-0]
    [IPU1-0] 261.435521 s: +++++++++++++++++pObj->chainsCfg->displayType = 7, pObj->displayWidth = 1920, pObj->displayHeight = 1200+++++++++++++++
    [IPU1-0] 261.446532 s: CAPTURE: Create in progress !!!
    [IPU1-0] 261.446806 s: CAPTURE: VIP1 Slice0 PortA capture mode is [ 8-bit] !!!
    [IPU1-0] 261.494723 s: CAPTURE: Create Done !!!
    [IPU1-0] 261.495089 s: IPC_OUT_0 : Create in progress !!!
    [IPU1-0] 261.495394 s: IPC_OUT_0 : Create Done !!!
    [HOST ] 261.495577 s: IPC_IN_0 : Create in progress !!!
    [HOST ] 261.495882 s: IPC_IN_0 : Create Done !!!
    [HOST ] 261.496095 s: ALGORITHM: Create in progress (algId = 11) !!!
    [HOST ] 261.502684 s: UTILS: DMA: Allocated CH (TCC) = 0 (0)
    [HOST ] 261.502714 s: UTILS: DMA: 0 of 1: Allocated PaRAM = 0 (0x43305600)
    [HOST ] 261.502714 s: ALGORITHM: Create Done (algId = 11) !!!
    [HOST ] 261.502806 s: IPC_OUT_1 : Create in progress !!!
    [HOST ] 261.502836 s: IPC_OUT_1 : Create Done !!!
    [EVE2 ] 261.503111 s: IPC_IN_0 : Create in progress !!!
    [EVE2 ] 261.504026 s: IPC_IN_0 : Create Done !!!
    [EVE2 ] 261.504605 s: ALGORITHM: Create in progress (algId = 14) !!!
    [IPU1-0] 262.779997 s: IPC_IN_1 : Create in progress !!!
    [IPU1-0] 262.781217 s: IPC_IN_1 : Create Done !!!
    [HOST ] 262.781400 s: IPC_OUT_0 : Create in progress !!!
    [HOST ] 262.781431 s: IPC_OUT_0 : Create Done !!!
    [EVE1 ] 262.781736 s: IPC_IN_0 : Create in progress !!!
    [EVE1 ] 262.782620 s: IPC_IN_0 : Create Done !!!
    [EVE1 ] 262.783200 s: ALGORITHM: Create in progress (algId = 14) !!!
    [EVE2 ] 262.778503 s: ALGORITHM: Create Done (algId = 14) !!!
    [EVE2 ] 262.779113 s: IPC_OUT_0 : Create in progress !!!
    [EVE2 ] 262.779601 s: IPC_OUT_0 : Create Done !!!
    [IPU1-0] 264.056091 s: IPC_IN_0 : Create in progress !!!
    [IPU1-0] 264.057311 s: IPC_IN_0 : Create Done !!!
    [IPU1-0] 264.057890 s: *************************Merge*************************
    [IPU1-0] 264.057982 s: *************************Display_VideoPrm.inQueParams.prevLinkId= 37 ,Display_VideoPrm.inQueParams.prevLinkQueId= 0 , Display_VideoPrm.displayId= 0 ,Display_VideoPrm.displayScanFormat= 1 ,Display_VideoPrm.rtParams.tarWidth= 1920 ,Display_VideoPrm.rtParams.tarHeight= 1200 ,Display_VideoPrm.rtParams.posX= 0 ,Display_VideoPrm.rtParams.posY= 0 ,*************************
    [IPU1-0] 264.058378 s: DISPLAY: Create in progress !!!
    [IPU1-0] 264.058744 s: dispcore/src/vpscore_dss.c @ Line 1369:
    [IPU1-0] 264.058836 s: Upscaling of greater than 8x is not supported
    [IPU1-0] 264.058927 s: dispdrv/src/vpsdrv_displayCore.c @ Line 295:
    [IPU1-0] 264.058988 s: Set DSS parameter failed
    [IPU1-0] 264.059049 s: Assertion @ Line: 346 in links_ipu/display/displayLink_drv.c: status==SYSTEM_LINK_STATUS_SOK : failed !!!
    [EVE1 ] 264.054260 s: ALGORITHM: Create Done (algId = 14) !!!
    [EVE1 ] 264.055206 s: IPC_OUT_0 : Create in progress !!!
    [EVE1 ] 264.055694 s: IPC_OUT_0 : Create Done !!!


    The log shows that the error occurred during the creation of DISPLAY. Do you konw how to sovle this problem?
    Thank you!


    UseCase: chains_tidlEve

    Capture -> Alg_tidlpreproc (A15)
    Alg_tidlpreproc (A15) -> Alg_tidl_1 (EVE1)
    Alg_tidlpreproc (A15) -> Alg_tidl_2 (EVE2)
    Alg_tidl_1 (EVE1) -> Merge (IPU1_0)
    Alg_tidl_2 (EVE2) -> Merge (IPU1_0)
    Merge (IPU1_0) -> Display_Video
    GrpxSrc -> Display_Grpx
  • Hi,

    You cannot directly display the output of the TIDL algorithm plug-in. The output is segment indices values between 0 and 4 each index representing a different segment like ROAD, VEHICLES, PEDESTRIAN, TRAFFIC SIGNAL.

    We have a post process alg plug-in which converts the TIDL output into UV plane which can be displayed.

    This alg plug-in will be part of the upcoming vision sdk release.

    regards,

    Anand

  • Hi Anand, what time do you will release the sdk?
  • Hi,

    It will be part of vsdk 3.01 which is due at end of September.

    regards,

    Anand

  • Hi Anand,
    Which day would the vsdk 3.01 be released?
  • Hi,

    it is expected to be released in Mid-Oct 2017.

    Regards,
    Yordan