TDA3: Phase constraint between CLK and DQS for DDR3

kenshow

Genius 3725 points

Part Number: TDA3

Hi,

Do you have information of phase constraint or the PCB rules between CLK and DQS for DDR3 of TDA3?

I haven't found the information in DM. If there are no information, please let me know the reason.

Regards,
Kenshow

over 6 years ago

0 Yordan Kamenov over 6 years ago

TI__Mastermind 42515 points

Hi Kenshow,

I have forwarded your question to the experts for comment.

Regards,
Yordan

0 Yordan Kamenov over 6 years ago in reply to Yordan Kamenov

TI__Mastermind 42515 points

Hi Kenshow,

I have feedback from DM team that they are not aware of any constraints or PCB rules between CK and DQS signals.
You can check also if this document can be useful:
www.ti.com/.../litabsmultiplefilelist.tsp

Regards,
Yordan

0 kenshow over 6 years ago in reply to Yordan Kamenov

Genius 3725 points

Hi Yordan,

Is it ok to understand that there is no problem as TDA3x receiving from DDR3L if delay design is done?
(In the case of TDA3x receiving, delay of DQS round trip and skew delay within DDR 3 L are added)

So, I am planning that the delay design is CLK - DQS = ± 0.18 [Tck] against tDQSS (CLK - DQS = ± 0.25 [Tck]) specified by JEDEC . Is this considering OK for with DDRL3 design of TDA3x?

Regards,
Kenshow

0 kenshow over 6 years ago in reply to kenshow

Genius 3725 points

Hi Yordan,

　I am waiting for your comment.

Regards,
Kenshow

0 Dian Iliev over 6 years ago in reply to kenshow

TI__Intellectual 1245 points

Hi Kenshow,

The Device supports JEDEC standard compliant DDR3 and DDR3L SDRAM devices, so as long as you cover the JEDEC spec requirements it should be ok.

Also please ensure your design employees Fly-By topology and follows the DDR3 Board Design and Layout Guidelines that are provided in the device DM. These guidelines are very important to ensure a proper DDR3 operation.

Thanks,
Dian

0 kenshow over 6 years ago in reply to Dian Iliev

Genius 3725 points

Hi Dian,

Thanks for your reply.

Regards,
Kenshow

Processors

Processors forum

TDA3: Phase constraint between CLK and DQS for DDR3