• State TI Thinks Resolved
  • Locked Locked
  • Replies 28 replies
  • Answers 7 answers
  • Subscribers 101 subscribers
  • Views 3712 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CCS/TDA2EVM5777: Vision SDK debugging on CCS

vikas patel
Prodigy 170 points
Part Number: TDA2EVM5777

Tool/software: Code Composer Studio

We are  trying to debug the Vision SDK code on CCS,   that we followed all steps mention in  section "3.8 Load using CCS" of  "Vision SDK TDA2xx User guide " document. and seeing expected output  in CCS in debug mode but not able to see anything on UART so could not be able to run some use-case and debug the code.

Are we missing anything in this setup?

Thanks

  • 0
    TI__Guru 55685 points
    Hi Vikas,

    What is the UART terminal setting? It should be 115200 baud rate, 8 bit data, parity none and stop bit 1.

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    Prodigy 170 points
    Yes Risabh everything is set up according to the document.
    We have already boot the H/W with SD card and execute the test cases and tis time we are trying to boot from CCS.
  • 0 in reply to vikas patel
    TI__Guru 55685 points
    Hi Vikas,

    Have you loaded executable for all the cores? Can you connect to A15 and see if it is waiting in IPC attach.
    If this is the case then one of the cores has not been loaded.

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    Prodigy 170 points
    Yes Rishabh, it's waiting in IPC attach.
    I have loaded this core with respectibe binaries..
    On ARP32_EVE_4, load the binary, “vision_sdk_arp32_4_release.xearp32F”.
    On ARP32_EVE_3, load the binary, “vision_sdk_arp32_3_release.xearp32F”.
    On ARP32_EVE_2, load the binary, “vision_sdk_arp32_2_release.xearp32F”.
    On ARP32_EVE_1, load the binary, “vision_sdk_arp32_1_release.xearp32F”.
    On C66xx_DSP2, load the binary, “vision_sdk_c66xdsp_2_release.xe66”.
    On C66xx_DSP1, load the binary, “vision_sdk_c66xdsp_1_release.xe66”.
    On Cortex_M4_IPU1_C0, load the binary, “vision_sdk_ipu1_0_release.xem4”.
    On Cortex_M4_IPU1_C1, load the binary, “vision_sdk_ipu1_1_release.xem4”.
    On CortexA15_0, load the binary, "vision_sdk_a15_0_debug.xa15fg”
    Do I need to load other core also?
  • 0 in reply to vikas patel
    TI__Guru 55685 points
    Hi Vikas,

    Can you please run the command "make showconfig" and share the results. You might have to load IPU2 binaries as well.

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    Prodigy 170 points

    Please find the make showconfig.

    Thanks

    Vikas

    8875.showconfig.txt 
    make -C /home/PROCESSOR_SDK_VISION_03_00_00_00/vision_sdk/apps/configs -f build_makeconfig.mk showconfig
make[1]: Entering directory `/home/PROCESSOR_SDK_VISION_03_00_00_00/vision_sdk/apps/configs'
#
# Build Config is [ tda2xx_evm_bios_all ]
# Build Config file is @ /home/PROCESSOR_SDK_VISION_03_00_00_00/vision_sdk/configs/tda2xx_evm_bios_all/cfg.mk
# Build Config .h file is @ /home/PROCESSOR_SDK_VISION_03_00_00_00/vision_sdk/links_fw/include/config/apps/tda2xx_evm_bios_all/system_cfg.h
# Build CPUs is @ all
#
# CPUs included in application,
# PROC_IPU1_0_INCLUDE=yes
# PROC_IPU1_1_INCLUDE=yes
# PROC_IPU2_INCLUDE=yes
# PROC_DSP1_INCLUDE=yes
# PROC_DSP2_INCLUDE=yes
# PROC_EVE1_INCLUDE=yes
# PROC_EVE2_INCLUDE=yes
# PROC_EVE3_INCLUDE=yes
# PROC_EVE4_INCLUDE=yes
# PROC_A15_0_INCLUDE=yes
#
# Platform config,
# VSDK_BOARD_TYPE=TDA2XX_EVM [options: TDA2XX_EVM TDA2EX_EVM TDA3XX_EVM TDA3XX_RVP]
# PLATFORM=tda2xx-evm
# DUAL_A15_SMP_BIOS=no
# DDR_MEM=DDR_MEM_512M [options: DDR_MEM_128M DDR_MEM_512M DDR_MEM_1024M]
# NDK_PROC_TO_USE=a15_0 [options: a15_0 ipu1_0 ipu1_1 ipu2 none]
# NSP_TFDTP_INCLUDE=no [options: yes no]
# FATFS_PROC_TO_USE=ipu1_0 [options: ipu1_0 none]
# RADAR_BOARD=none [options: TDA3XX_AR12_ALPS TDA3XX_AR12_VIB_DAB_BOOSTER TDA3XX_RADAR_RVP none]
#
# Build config,
# BUILD_OS=Linux [options: Windows_NT Linux]
# BUILD_DEPENDENCY_ALWAYS=no
# BUILD_ALGORITHMS=no
# BUILD_INFOADAS=no
# PROFILE=release [options: debug release]
# KW_BUILD=no
# CPLUSPLUS_BUILD=no
# IPU_PRIMARY_CORE=ipu1_0 [options: ipu1_0 ipu2]
# IPU_SECONDARY_CORE=ipu2 [options: ipu1_0 ipu2]
# A15_TARGET_OS=Bios [options: Bios Linux Qnx]
# BSP_STW_PACKAGE_SELECT=all [options: all vps-iss-dss-only vps-vip-vpe]
#
# Safety Module config,
# RTI_INCLUDE=no
# ECC_FFI_INCLUDE=no
# DCC_ESM_INCLUDE=no
#
# Video Module config,
# IVAHD_INCLUDE=yes
# VPE_INCLUDE=yes
# CAL_INCLUDE=no
# ISS_INCLUDE=no
# ISS_ENABLE_DEBUG_TAPS=no
# WDR_LDC_INCLUDE=no
# DSS_INCLUDE=yes
#
# Open Compute config,
# OPENCL_INCLUDE=no
# TARGET_ROOTDIR=/home/PROCESSOR_SDK_VISION_03_00_00_00/vision_sdk/apps/src/rtos/opencl
# ENABLE_OPENCV=no
# ENABLE_OPENCV_TESTS=no
# OPENVX_INCLUDE=yes
#
# Log config,
# ENABLE_UART_LOG=yes
# ENABLE_NETWORK_LOG=no
# ENABLE_CCS_LOG=no
# CIO_REDIRECT=yes
#
# IPC config,
# WORKQ_INCLUDE=no
# IPC_LIB_INCLUDE=no
#
# Surround View config,
# SRV_FAST_BOOT_INCLUDE=no
#
# Other Module config,
# AVB_INCLUDE=no
# DCAN_INCLUDE=no
# RADAR_INCLUDE=no
# CPU_IDLE_ENABLED=yes
# FAST_BOOT_INCLUDE=no
# DATA_VIS_INCLUDE=no
# HS_DEVICE=no
# ULTRASONIC_INCLUDE=no
#
# Linux config,
# DEFAULT_UBOOT_CONFIG=dra7xx_evm_vision_config
# DEFAULT_KERNEL_CONFIG=omap2plus_defconfig
# DEFAULT_DTB=dra7-evm-infoadas.dtb
# CMEM_INCLUDE=no
# IPUMM_INCLUDE=no
# IPU1_EVELOADER_INCLUDE=no
# ROBUST_RVC_INCLUDE=no
# BUILD_ADAM_CAR=no
#
# Alg plugins included in build,
# ALG_autocalibration ALG_autoremap ALG_census ALG_clr ALG_denseopticalflow ALG_disparityhamdist ALG_dmaSwMs ALG_edgedetection ALG_framecopy ALG_lanedetection ALG_objectdetection ALG_remapmerge ALG_safe_framecopy ALG_sfm ALG_sparseopticalflow ALG_stereo_postprocessing ALG_subframecopy ALG_surroundview ALG_openvx ALG_tidl
#
# Use-cases included in build,
# UC_srv_calibration UC_lvds_vip_dual_cam_dual_display UC_lvds_vip_multi_cam_view UC_lvds_vip_sv_analytics_us UC_lvds_vip_sv_standalone UC_lvds_vip_single_stereo UC_lvds_vip_single_stereo_auto_calib UC_lvds_vip_single_stereo_calibration UC_network_rx_tx UC_network_stereo_display UC_ov490_vip_sv_standalone UC_saveDisFrame UC_vip_single_cam_analytics2 UC_vip_single_cam_dense_optical_flow UC_vip_single_cam_dual_display UC_vip_single_cam_edge_detection UC_vip_single_cam_frame_copy UC_vip_single_cam_frame_copy_safety UC_vip_single_cam_lane_detection UC_vip_single_cam_object_detection2 UC_vip_single_cam_sfm UC_vip_single_cam_sparse_optical_flow UC_vip_single_cam_subframe_copy UC_vip_single_cam_tlr UC_vip_single_cam_view UC_vip_single_cam_view_encdec UC_vip_single_cam_openvx UC_tidl
#
make -s -fbuild_makeconfig.mk check_cpu_include
make[2]: Entering directory `/home/PROCESSOR_SDK_VISION_03_00_00_00/vision_sdk/apps/configs'
#
# CPUs that are NOT required but included in config [ tda2xx_evm_bios_all ],
#
# WARNING: IPU1_1 can be excluded from application
# WARNING: IPU2 can be excluded from application
# WARNING: EVE4 can be excluded from application
#
# CPUs that are required but not included in config [ tda2xx_evm_bios_all ],
#
#
# Edit /home/PROCESSOR_SDK_VISION_03_00_00_00/vision_sdk/build/configs/tda2xx_evm_bios_all/cfg.mk to include or exclude CPUs in an application
#
make[2]: Leaving directory `/home/PROCESSOR_SDK_VISION_03_00_00_00/vision_sdk/apps/configs'
make[1]: Leaving directory `/home/PROCESSOR_SDK_VISION_03_00_00_00/vision_sdk/apps/configs'

  • 0 in reply to vikas patel
    TI__Guru 55685 points
    Hi Vikas,

    IPU2 is enabled in the config. IPU2 runs in SMP mode so you need to load same IPU2 binary on both IPU2_0 and IPU2_1 core.
    Then you should be able to run VSDK via CCS loading.

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    Intellectual 330 points

    Hi Rishabh,

    As you have suggested i run the showconfig command and i checked the logs in that IPU2 is not enabled so we don't need to load the binaries.

    Please go through below logs which i got after running "make showconfig" command.

    Showconfig_result.doc

    Regards,

    Pritam

  • 0 in reply to Pritam Patil57
    TI__Guru 55685 points
    Hi Pritam,

    Can you connect to all the cores that are enabled in your configuration and check their state.
    It seems that one of the cores has aborted.
    Most likely the core to abort should be IPU.
    If this is the case you need to set VISION_SDK_CONFIG to 1 in TDA2xx Multicore gel script.

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    Intellectual 330 points
    Hi Rishabh,

    I have loaded all binaries whose cores are shown enabled in "make showconfig",and after loading binaries it is waiting for IPU attach.
    And as mentioned in document I have set VISION_SDK_CONFIG flag value to '1'.
    And all cores are in running state after loading respective cores binary.

    I am using following tools and hardware configurations :
    OS : Ubuntu 14.04 LTS
    Emulator :Spectrum Digital XDS560V2 STM USM Traveler
    Board : TDA2x
    Uart settings : Data Rate : 115.2 kbps,Data Length : 8 bit,stop bit : 1 bit,Parity :None

    Regards,
    Pritam
  • 0 in reply to Pritam Patil57
    TI__Guru 55685 points
    Hi Pritam,

    This seems strange.
    Can you arrange for a webex session tomorrow at 1 pm IST.

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    Intellectual 330 points
    Hi Rishabh,

    I have sent you a request ... please accept it i will send you meeting invitation link.

    Regards,
    Pritam
  • 0 in reply to Pritam Patil57
    TI__Guru 55685 points
    Hi Pritam,

    I have accepted, kindly send the invite.

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    TI__Guru 55685 points
    Call Summary:
    IPU2 binary was not loaded due to which IPC attach did not complete. IPU2_C0 and IPU2_C1 both should be set as a synchronized pair and then binary should be loaded for synchronized group.
    It seems that there is an issue with VSDK 3.1 where IPU2 is enabled in build but "make showconfig" shows that IPU2 is disabled. TI will investigate this and fix it in upcoming release.

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    Intellectual 330 points

    Hi Rishabh,

    As per our discussion on call and changes you have suggested on mail i made changes but i got error while loading binary of IPU2_C0 / C1 (please find attached image.)

    I checked twice but got same result,i am using vision_sdk 3.1 version.

    Also on serial port i didn't receive any data.

    Regards,

    Pritam

  • 0 in reply to Pritam Patil57
    TI__Guru 55685 points

    Hi Pritam,

    It seems that you have loaded binary for IPU2_C0 and IPU2_C1 individually.
    Can you run by loading binary for the group and not the individual cores.

    Regards,
    Rishabh

  • 0 in reply to Rishabh Garg
    TI__Guru 55685 points
    Hi Pritam,

    The issue is with the build target.
    You might have first built the apps and later on changed MAKEAPPNAME to sample_app.
    Can you please confirm whether you want to build sample_app or apps.
    You should set MAKEAPPNAME accordingly and try a clean build.
    Note that IPU2 is not included in sample app and hence there is no need to load it.

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    Intellectual 330 points

    8715.Console.txt 
    Cortex_M4_IPU1_C0: GEL Output: --->>> TDA2xx Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> TDA2xx Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> TDA2xx Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> TDA2xx Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU2_C0: GEL Output: --->>> TDA2xx Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU2_C0: GEL Output: --->>> TDA2xx Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU2_C1: GEL Output: --->>> TDA2xx Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU2_C1: GEL Output: --->>> TDA2xx Cortex M4 Startup Sequence DONE! <<<---
C66xx_DSP1: GEL Output: --->>> TDA2xx C66x DSP Startup Sequence In Progress... <<<---
C66xx_DSP1: GEL Output: --->>> TDA2xx C66x DSP Startup Sequence DONE! <<<---
C66xx_DSP2: GEL Output: --->>> TDA2xx C66x DSP Startup Sequence In Progress... <<<---
C66xx_DSP2: GEL Output: --->>> TDA2xx C66x DSP Startup Sequence DONE! <<<---
CortexA15_0: GEL Output: --->>> TDA2xx Cortex A15 Startup Sequence In Progress... <<<---
CortexA15_0: GEL Output: --->>> TDA2xx Cortex A15 Startup Sequence DONE! <<<---
ARP32_EVE_1: GEL Output: --->>> Configuring EVE Memory Map <<<---
ARP32_EVE_1: GEL Output: --->>> EVE Memory Map Done! <<<---
ARP32_EVE_2: GEL Output: --->>> Configuring EVE Memory Map <<<---
ARP32_EVE_2: GEL Output: --->>> EVE Memory Map Done! <<<---
ARP32_EVE_3: GEL Output: --->>> Configuring EVE Memory Map <<<---
ARP32_EVE_3: GEL Output: --->>> EVE Memory Map Done! <<<---
ARP32_EVE_4: GEL Output: --->>> Configuring EVE Memory Map <<<---
ARP32_EVE_4: GEL Output: --->>> EVE Memory Map Done! <<<---
IcePick_D: GEL Output: Ipu RTOS is released from Wait-In-Reset. 
IcePick_D: GEL Output: Ipu SIMCOP is released from Wait-In-Reset. 
IcePick_D: GEL Output: IVAHD C66 is released from Wait-In-Reset. 
IcePick_D: GEL Output: IVAHD ICONT1 is released from Wait-In-Reset. 
IcePick_D: GEL Output: IVAHD ICONT2 is released from Wait-In-Reset. 
CS_DAP_DebugSS: GEL Output: --->>> CONFIGURE DEBUG DPLL settings to 1.9 GHZs  <<<---
CS_DAP_DebugSS: GEL Output: > Setup DebugSS 1.9GHz in progress...
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz 
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS PLL Clocking 1.9GHz 
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS ATB Clocking 380MHz 
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz 
CS_DAP_DebugSS: GEL Output: --->>> TURNING ON L3_INSTR and L3_3 clocks required for debug instrumention <<<<<<----
CS_DAP_DebugSS: GEL Output: ---<<< L3 instrumentation clocks are enabled >>>> ---
CS_DAP_DebugSS: GEL Output: --->>> Mapping TIMER supsend sources to default cores <<<<<<----
CS_DAP_PC: GEL Output: Cortex-A15 1 is not in WIR mode so nothing to do.
CortexA15_0: GEL Output: --->>> TDA2xx Target Connect Sequence Begins ... <<<---
CortexA15_0: GEL Output: 	--->>> TDA2xx PG2.0 GP device <<<---
CortexA15_0: GEL Output: 	--->>> The core is in non-SECURE state. <<<---
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<---
CortexA15_0: GEL Output: 	Cortex A15 DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	Cortex A15 DPLL is already locked, now unlocking...  
CortexA15_0: GEL Output: 	Cortex A15 DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	IVA DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	IVA DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	PER DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: 	PER DPLL already locked, now unlocking  
CortexA15_0: GEL Output: 	PER DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	CORE DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	CORE DPLL OPP  already locked, now unlocking....  
CortexA15_0: GEL Output: 	CORE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	ABE DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: 	ABE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	GMAC DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	GMAC DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	GPU DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	GPU DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	DSP DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	DSP DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	EVE DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	EVE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	PCIE_REF DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	PCIE_REF DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<---
CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: 	DDR DPLL clock config for 532MHz is in progress...
CortexA15_0: GEL Output: 	DDR DPLL clock config for 532MHz is in DONE!
CortexA15_0: GEL Output:        Launch full leveling
CortexA15_0: GEL Output:        Updating slave ratios in PHY_STATUSx registers
CortexA15_0: GEL Output:        as per HW leveling output
CortexA15_0: GEL Output:        HW leveling is now disabled. Using slave ratios from 
CortexA15_0: GEL Output:        PHY_STATUSx registers
CortexA15_0: GEL Output:        Launch full leveling
CortexA15_0: GEL Output:        Updating slave ratios in PHY_STATUSx registers
CortexA15_0: GEL Output:        as per HW leveling output
CortexA15_0: GEL Output:        HW leveling is now disabled. Using slave ratios from 
CortexA15_0: GEL Output:        PHY_STATUSx registers
CortexA15_0: GEL Output:        One EMIF - 512MB total memory
CortexA15_0: GEL Output:        Same memory mapped at 0x80000000 and 0xA0000000
CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> TDA2xx Begin All Pad Configuration for Vision Platform <<<---
CortexA15_0: GEL Output: --->>> TDA2xx Begin All Pad Configuration for RGMII usage on EVM Platform <<<---
CortexA15_0: GEL Output: 	--->>> TDA2xx Begin GMAC_SW MDIO Pad Configuration <<<---
CortexA15_0: GEL Output: 	--->>> TDA2xx End GMAC_SW MDIO Pad Configuration <<<---
CortexA15_0: GEL Output: 	--->>> TDA2xx Begin GMAC_SW RGMII0 Pad Configuration <<<---
CortexA15_0: GEL Output: 	--->>> TDA2xx End GMAC_SW RGMII0 Pad Configuration <<<---
CortexA15_0: GEL Output: 	--->>> TDA2xx Begin GMAC_SW RGMII1 Pad Configuration <<<---
CortexA15_0: GEL Output: 	--->>> TDA2xx End GMAC_SW RGMII1 Pad Configuration <<<---
CortexA15_0: GEL Output: --->>> TDA2xx End All Pad Configuration for RGMII usage on EVM Platform <<<---
CortexA15_0: GEL Output: --->>> TDA2xx End All Pad Configuration for Vision Platform <<<---
CortexA15_0: GEL Output: --->>> TDA2xx Target Connect Sequence DONE !!!!!  <<<---
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... 
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! 
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... 
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! 
CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> EVE1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: DEBUG: Resetting EVE MMU ... 
CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 1: 0x00000000 --> 0x40500000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 2: 0x80000000 --> 0x80000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 3: 0x81000000 --> 0x81000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 4: 0x82000000 --> 0x82000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 5: 0x83000000 --> 0x83000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 6: 0x84000000 --> 0x84000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 7: 0x85000000 --> 0x85000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 8: 0x86000000 --> 0x86000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 9: 0x87000000 --> 0x87000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 10: 0x40000000 --> 0x40000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 11: 0x4A000000 --> 0x4A000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 12: 0x45000000 --> 0x45000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 13: 0x48000000 --> 0x48000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE1 MMU0 TLB entry 14: 0x42000000 --> 0x42000000  
CortexA15_0: GEL Output: --->>> EVE1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> EVE2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: DEBUG: Resetting EVE MMU ... 
CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 1: 0x00000000 --> 0x40500000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 2: 0x80000000 --> 0x80000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 3: 0x81000000 --> 0x81000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 4: 0x82000000 --> 0x82000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 5: 0x83000000 --> 0x83000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 6: 0x84000000 --> 0x84000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 7: 0x85000000 --> 0x85000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 8: 0x86000000 --> 0x86000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 9: 0x87000000 --> 0x87000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 10: 0x40000000 --> 0x40000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 11: 0x4A000000 --> 0x4A000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 12: 0x45000000 --> 0x45000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 13: 0x48000000 --> 0x48000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE2 MMU0 TLB entry 14: 0x42000000 --> 0x42000000  
CortexA15_0: GEL Output: --->>> EVE2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> EVE3SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: DEBUG: Resetting EVE MMU ... 
CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 1: 0x00000000 --> 0x40500000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 2: 0x80000000 --> 0x80000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 3: 0x81000000 --> 0x81000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 4: 0x82000000 --> 0x82000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 5: 0x83000000 --> 0x83000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 6: 0x84000000 --> 0x84000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 7: 0x85000000 --> 0x85000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 8: 0x86000000 --> 0x86000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 9: 0x87000000 --> 0x87000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 10: 0x40000000 --> 0x40000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 11: 0x4A000000 --> 0x4A000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 12: 0x45000000 --> 0x45000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 13: 0x48000000 --> 0x48000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE3 MMU0 TLB entry 14: 0x42000000 --> 0x42000000  
CortexA15_0: GEL Output: --->>> EVE3SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> EVE4SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: DEBUG: Resetting EVE MMU ... 
CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 1: 0x00000000 --> 0x40500000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 2: 0x80000000 --> 0x80000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 3: 0x81000000 --> 0x81000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 4: 0x82000000 --> 0x82000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 5: 0x83000000 --> 0x83000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 6: 0x84000000 --> 0x84000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 7: 0x85000000 --> 0x85000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 8: 0x86000000 --> 0x86000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 9: 0x87000000 --> 0x87000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 10: 0x40000000 --> 0x40000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 11: 0x4A000000 --> 0x4A000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 12: 0x45000000 --> 0x45000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 13: 0x48000000 --> 0x48000000  
CortexA15_0: GEL Output: DEBUG: Configuring EVE4 MMU0 TLB entry 14: 0x42000000 --> 0x42000000  
CortexA15_0: GEL Output: --->>> EVE4SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---
Cortex_M4_IPU2_C0: GEL Output: Core Reset has occurred.

Cortex_M4_IPU2_C1: GEL Output: Core Reset has occurred.

Cortex_M4_IPU2_C0: GEL Output: Core Reset has occurred.

Cortex_M4_IPU2_C1: GEL Output: Core Reset has occurred.

Cortex_M4_IPU1_C0: GEL Output: Core Reset has occurred.

Cortex_M4_IPU1_C1: GEL Output: Core Reset has occurred.

CortexA15_0: GEL Output: --->>> Reset occurs <<<---
CortexA15_0: GEL Output: 	--->>> TDA2xx PG2.0 GP device <<<---
Cortex_M4_IPU2_C1: Trouble Setting Breakpoint with the Action "Process CIO" at 0x850289ae: (Error -1067 @ 0x850289AE) There is already a breakpoint at the requested address. This error may be caused by a shared memory SMP configuration. You may consider setting up shared memory in the memory map. (Emulation package 7.0.48.0) 
Cortex_M4_IPU2_C1: Breakpoint Manager: Retrying with a AET breakpoint
Cortex_M4_IPU2_C1: Breakpoint Manager: Error enabling this function: Address exceeds the allowed range
Cortex_M4_IPU2_C1: Trouble Setting Breakpoint with the Action "Terminate Program Execution" at 0x85029d94: (Error -1067 @ 0x85029D94) There is already a breakpoint at the requested address. This error may be caused by a shared memory SMP configuration. You may consider setting up shared memory in the memory map. (Emulation package 7.0.48.0) 
Cortex_M4_IPU2_C1: Breakpoint Manager: Retrying with a AET breakpoint
Cortex_M4_IPU2_C1: Breakpoint Manager: Error enabling this function: Address exceeds the allowed range
Cortex_M4_IPU2_C1: Trouble Setting Breakpoint with the Action "Remain Halted" at 0x85019afc: (Error -1067 @ 0x85019AFC) There is already a breakpoint at the requested address. This error may be caused by a shared memory SMP configuration. You may consider setting up shared memory in the memory map. (Emulation package 7.0.48.0) 
Cortex_M4_IPU2_C1: Trouble Removing Breakpoint with the Action "Remain Halted" at 0x85019afc: (Error -2044 @ 0x85019AFC) Internal error: Requested breakpoint does not exist. Restart the application. If error persists, please report the error. (Emulation package 7.0.48.0) 
Cortex_M4_IPU2_C1: Trouble Setting Breakpoint with the Action "Terminate Program Execution" at 0x85029d94: (Error -1067 @ 0x85029D94) There is already a breakpoint at the requested address. This error may be caused by a shared memory SMP configuration. You may consider setting up shared memory in the memory map. (Emulation package 7.0.48.0) 
Cortex_M4_IPU2_C1: Trouble Removing Breakpoint with the Action "Terminate Program Execution" at 0x85029d94: (Error -2044 @ 0x85029D94) Internal error: Requested breakpoint does not exist. Restart the application. If error persists, please report the error. (Emulation package 7.0.48.0) 
Cortex_M4_IPU2_C1: Trouble Setting Breakpoint with the Action "Process CIO" at 0x850289ae: (Error -1067 @ 0x850289AE) There is already a breakpoint at the requested address. This error may be caused by a shared memory SMP configuration. You may consider setting up shared memory in the memory map. (Emulation package 7.0.48.0) 
Cortex_M4_IPU2_C1: Breakpoint Manager: Retrying with a AET breakpoint
Cortex_M4_IPU2_C1: Breakpoint Manager: Error enabling this function: Address exceeds the allowed range
Cortex_M4_IPU2_C1: Trouble Setting Breakpoint with the Action "Terminate Program Execution" at 0x85029d94: (Error -1067 @ 0x85029D94) There is already a breakpoint at the requested address. This error may be caused by a shared memory SMP configuration. You may consider setting up shared memory in the memory map. (Emulation package 7.0.48.0) 
Cortex_M4_IPU2_C1: Breakpoint Manager: Retrying with a AET breakpoint
Cortex_M4_IPU2_C1: Breakpoint Manager: Error enabling this function: Address exceeds the allowed range
Cortex_M4_IPU2_C1: Trouble Setting Breakpoint with the Action "Finish Auto Run" at 0x85019afc: (Error -1067 @ 0x85019AFC) There is already a breakpoint at the requested address. This error may be caused by a shared memory SMP configuration. You may consider setting up shared memory in the memory map. (Emulation package 7.0.48.0) 
Cortex_M4_IPU2_C1: Trouble Removing Breakpoint with the Action "Finish Auto Run" at 0x85019afc: (Error -2044 @ 0x85019AFC) Internal error: Requested breakpoint does not exist. Restart the application. If error persists, please report the error. (Emulation package 7.0.48.0)
    Hi Rishabh,

    I am building for apps,and same changes are made in Rules.mk file for MAKEAPPNAME in build folder.

    Before building through gmake command i used "make clean" command and run "gmake -s -j depend" command.

    And after building app through gmake command new binary files created in "/vision_sdk/vision_sdk/binaries/apps/tda2xx_evm_bios_all/vision_sdk/bin/tda2xx-evm"

    I ungrouped all cores and created IPU2_C0 and IPU2_C1 synchronous pair  and when i try to load binary for IPU2 i got error.

    I have also attached console output which i am getting when i try to load binary file of IPU2.

    Regards,

    Pritam

  • 0 in reply to Pritam Patil57
    TI__Guru 55685 points
    Hi Pritam,

    Can you share the output of make showconfig.

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    Intellectual 330 points

    Make showconfig.txt 
    ~/vision_sdk/vision_sdk/build$ make showconfig
make -C /home/anshul/vision_sdk/vision_sdk/apps/configs -f build_makeconfig.mk showconfig
make[1]: Entering directory `/home/anshul/vision_sdk/vision_sdk/apps/configs'
#
# Build Config is [ tda2xx_evm_bios_all ]
# Build Config file is @ /home/anshul/vision_sdk/vision_sdk/configs/tda2xx_evm_bios_all/cfg.mk
# Build Config .h file is @ /home/anshul/vision_sdk/vision_sdk/links_fw/include/config/apps/tda2xx_evm_bios_all/system_cfg.h
# Build CPUs is @ all
#
# CPUs included in application,
# PROC_IPU1_0_INCLUDE=yes
# PROC_IPU1_1_INCLUDE=yes
# PROC_IPU2_INCLUDE=yes
# PROC_DSP1_INCLUDE=yes
# PROC_DSP2_INCLUDE=yes
# PROC_EVE1_INCLUDE=yes
# PROC_EVE2_INCLUDE=yes
# PROC_EVE3_INCLUDE=yes
# PROC_EVE4_INCLUDE=yes
# PROC_A15_0_INCLUDE=yes
#
# Platform config,
# VSDK_BOARD_TYPE=TDA2XX_EVM [options: TDA2XX_EVM TDA2EX_EVM TDA3XX_EVM TDA3XX_RVP]
# PLATFORM=tda2xx-evm
# DUAL_A15_SMP_BIOS=no
# DDR_MEM=DDR_MEM_512M [options: DDR_MEM_128M DDR_MEM_512M DDR_MEM_1024M]
# NDK_PROC_TO_USE=ipu1_1 [options: a15_0 ipu1_0 ipu1_1 ipu2 none]
# NSP_TFDTP_INCLUDE=no [options: yes no]
# TDA2EX_ETHSRV_BOARD=no [options: yes no]
# FATFS_PROC_TO_USE=ipu1_0 [options: ipu1_0 none]
# RADAR_BOARD=none [options: TDA3XX_AR12_ALPS TDA3XX_AR12_VIB_DAB_BOOSTER TDA3XX_RADAR_RVP none]
#
# Build config,
# BUILD_OS=Linux [options: Windows_NT Linux]
# BUILD_DEPENDENCY_ALWAYS=no
# BUILD_ALGORITHMS=no
# BUILD_INFOADAS=no
# PROFILE=release [options: debug release]
# KW_BUILD=no
# CPLUSPLUS_BUILD=no
# IPU_PRIMARY_CORE=ipu1_0 [options: ipu1_0 ipu2]
# IPU_SECONDARY_CORE=ipu2 [options: ipu1_0 ipu2]
# A15_TARGET_OS=Bios [options: Bios Linux Qnx]
# BSP_STW_PACKAGE_SELECT=all [options: all vps-iss-dss-only vps-vip-vpe]
#
# Safety Module config,
# RTI_INCLUDE=no
# ECC_FFI_INCLUDE=no
# DCC_ESM_INCLUDE=no
#
# Video Module config,
# IVAHD_INCLUDE=yes
# VPE_INCLUDE=yes
# CAL_INCLUDE=no
# ISS_INCLUDE=no
# ISS_ENABLE_DEBUG_TAPS=no
# WDR_LDC_INCLUDE=no
# DSS_INCLUDE=yes
#
# Open Compute config,
# OPENCL_INCLUDE=no
# TARGET_ROOTDIR=/home/anshul/vision_sdk/vision_sdk/apps/src/rtos/opencl
# ENABLE_OPENCV=no
# ENABLE_OPENCV_TESTS=no
# OPENVX_INCLUDE=yes
#
# Log config,
# ENABLE_UART_LOG=yes
# ENABLE_NETWORK_LOG=no
# ENABLE_CCS_LOG=no
# CIO_REDIRECT=yes
#
# IPC config,
# WORKQ_INCLUDE=no
# IPC_LIB_INCLUDE=no
#
# Surround View config,
# SRV_FAST_BOOT_INCLUDE=no
#
# Other Module config,
# AVB_INCLUDE=no
# DCAN_INCLUDE=no
# RADAR_INCLUDE=no
# CPU_IDLE_ENABLED=yes
# FAST_BOOT_INCLUDE=no
# DATA_VIS_INCLUDE=no
# HS_DEVICE=no
# ULTRASONIC_INCLUDE=no
#
# Linux config,
# DEFAULT_UBOOT_CONFIG=dra7xx_evm_vision_config
# DEFAULT_KERNEL_CONFIG=omap2plus_defconfig
# DEFAULT_DTB=dra7-evm-infoadas.dtb
# CMEM_INCLUDE=no
# IPUMM_INCLUDE=no
# IPU1_EVELOADER_INCLUDE=no
# ROBUST_RVC_INCLUDE=no
# BUILD_ADAM_CAR=no
#
# Alg plugins included in build,
# ALG_autocalibration ALG_autoremap ALG_census ALG_clr ALG_denseopticalflow ALG_disparityhamdist ALG_dmaSwMs ALG_edgedetection ALG_framecopy ALG_lanedetection ALG_objectdetection ALG_remapmerge ALG_safe_framecopy ALG_sfm ALG_sparseopticalflow ALG_stereo_postprocessing ALG_subframecopy ALG_surroundview ALG_openvx ALG_tidl
#
# Use-cases included in build,
# UC_srv_calibration UC_lvds_vip_dual_cam_dual_display UC_lvds_vip_multi_cam_view UC_lvds_vip_sv_analytics_us UC_lvds_vip_sv_standalone UC_lvds_vip_single_stereo UC_lvds_vip_single_stereo_auto_calib UC_lvds_vip_single_stereo_calibration UC_network_rx_tx UC_network_stereo_display UC_ov490_vip_sv_standalone UC_saveDisFrame UC_vip_single_cam_analytics2 UC_vip_single_cam_dense_optical_flow UC_vip_single_cam_dual_display UC_vip_single_cam_edge_detection UC_vip_single_cam_frame_copy UC_vip_single_cam_frame_copy_safety UC_vip_single_cam_lane_detection UC_vip_single_cam_object_detection2 UC_vip_single_cam_sfm UC_vip_single_cam_sparse_optical_flow UC_vip_single_cam_subframe_copy UC_vip_single_cam_tlr UC_vip_single_cam_view UC_vip_single_cam_view_encdec UC_vip_single_cam_openvx UC_tidl UC_semSeg
#
make -s -fbuild_makeconfig.mk check_cpu_include
make[2]: Entering directory `/home/anshul/vision_sdk/vision_sdk/apps/configs'
#
# CPUs that are NOT required but included in config [ tda2xx_evm_bios_all ],
#
# WARNING: IPU2 can be excluded from application
#
# CPUs that are required but not included in config [ tda2xx_evm_bios_all ],
#
#
# Edit /home/anshul/vision_sdk/vision_sdk/build/configs/tda2xx_evm_bios_all/cfg.mk to include or exclude CPUs in an application
#
make[2]: Leaving directory `/home/anshul/vision_sdk/vision_sdk/apps/configs'
make[1]: Leaving directory `/home/anshul/vision_sdk/vision_sdk/apps/configs'
anshul@punecpu173:~/vision_sdk/vision_sdk/build$
    Hi Rishabh,

    Please find attached file containing output of make showconfig.

    Regards,

    Pritam

  • 0 in reply to Pritam Patil57
    TI__Guru 55685 points
    Hi Pritam,

    I will try this at my end to check if there is any issue with IPU2.
    Meanwhile can you make PROC_IPU2_INCLUDE=no in configs/tda2xx_evm_bios_all/cfg.mk and try.

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    Intellectual 330 points

    Hi Rishabh,

    I have checked by making PROC_IPU2_INCLUDE=no in cfg.mk file but still getting error.

    Regards,

    Pritam

  • 0 in reply to Pritam Patil57
    TI__Guru 55685 points

    Hi Pritam,

    There is a script that you can use to load using CCS: <vision_sdk>\build\rtos\scripts\launch_visionsdk_tda2xx.js.
    You need to update configFilePath and baseDir defined in this script along with cores that are enabled in build.
    Kindly try this. Also can you share the gel files you are using.

    Regards,
    Rishabh

  • 0 in reply to Rishabh Garg
    Intellectual 330 points

    TDA2x.zipHi Rishabh,

    I checked with script file you have suggested,load that file into ccs with loadJSFile command,so following are my observations :

    1) When all cores all enabled then nothing comes on terminal for apps.

    2) Later i keep only core IPU1_0,IPU1_1, A15_0, dsp1 and dsp2 enabled then on terminal i am able to see usecases and able to run.Rest of cores i disabled (IPU2,EVE1,EVE2,EVE3,EVE4)

    I am using gel files from directory : "/ti/ccsv7/ccs_base/emulation/gel/TDA2x"

    Please find attached zip file containing gel files i am using.

    Regards,

    Pritam

  • 0 in reply to Pritam Patil57
    TI__Guru 55685 points

    Hi Pritam,

    Can you replace TDA2xx_ARP32_startup.gel with attached gel file and enable all EVEs.

    TDA2xx_ARP32_startup.gel

    Regards,

    Rishabh

  • 0 in reply to Rishabh Garg
    TI__Guru 55685 points
    Hi Pritam,

    I haven’t heard back from you, I’m assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out)

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    Intellectual 330 points
    Hi Rishabh,

    Sorry, for updating you the status so late .....!
    I tried with the .gel files you have suggested and also enabled all EVE cores but still stuck there only so i kept that task aside and working on other task.
    so once i finish my current task i will again look for this issue....!

    Regards,
    Pritam
  • 0 in reply to Pritam Patil57
    TI__Guru 55685 points
    Hi Pritam,

    Ok thanks for the update.

    Regards,
    Rishabh