Other Parts Discussed in Thread: TDA2
Hello
Why in TDA2EVM , DDR data pin connection are not in sequence?
for example: U65 DQ15(A3) connect to DDR_D14 , DQ14(B8) connect to DDR_D9?
thank you
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Hello
Why in TDA2EVM , DDR data pin connection are not in sequence?
for example: U65 DQ15(A3) connect to DDR_D14 , DQ14(B8) connect to DDR_D9?
thank you
Hi,
When interfacing TDA2 to DDR3, the DQ bits can be swapped within a byte lane to ease routing on the PCB.
Thus, the EVM design routed DQ15(A3) to DDR_D14 and DQ14(B8) to DDR_D9 , etc. because these mappings alleviated the challenges of the PCB routing.
Please note that DQ bit swapping can only be done within a byte lane.
Best regards,
Kevin