Accordingly to AM335x Datasheet, section 4.2.1, "OSC1 is disabled by default after power is applied. This clock input [(CLK_32K_RTC)] is optional and may not be required if the RTC is configured to receive a clock from the internal 32k RC oscillator (CLK_RC32K) or peripheral PLL (CLK_32KHZ) which receives a reference clock from the OSC0 input."First question is: how to enable OSC1?
Second: looking at TRM, section 126.96.36.199.12 figure 8.17, it seems that RTC clock source can be CLK_32K_RTC or CLK_32KHZ, depending on RTC.OSC_REG.32KCLK_SEL register bit setting (default at reset is 0, i.e. use CLK_32KHZ). Therefore it seems not possible to use the CLK_32K: is it correct my understanding?This seems evident also reading TRM section 20.3 about RTC_SS. But subsection 188.8.131.52, Clock Source, makes me further doubts:
"The clock reference for the RTC is an internal 32.768-kHz crystal or an external clock source of the same frequency. The source for the RTC reference clock may be provided by a crystal or by an external clock source. The RTC has an internal oscillator buffer to support direct operation with a crystal. The crystal is connected between pins RTC_XTALIN and RTC_XTALOUT. RTC_XTALIN is the input to the on-chip oscillator and RTC_XTALOUT is the output from the oscillator back to the crystal. The oscillator can be enabled or disabled by using the control module register rcosc_ctrl."
Which oscillator will be enaled/disabled using the rcosc_ctrl register (default at reset 0, i.e. osc active)? Is it the OSC1 or the on-chip 32K RC OSC used to generate the CLK_32K?
Looking at Linux Kernel source code, am335x_rtc_init function calls writel(0x48, base + 0x54), that is turn on bit 3 (32KCLK_SEL) and bit 7 (reserved) on RTC OSC_REG register. In this way RTC is configured to use the CLK_32K_RTC source, but what is bit 7 used for? There is no description on TRM...
Thanks for any clarification.
Max, thanks for the details in your post. It looks like there are some errors in both the DM and TRM, so let me clarify some things:
The RTC can only receive a clock from the 32KHz oscillator (CLK_32K_RTC), or the Peripheral PLL (CLK_32KHz). This is selected using RTC.OSC_REG.32KCLK_SEL register. Note this register refers to an internal clock source aux_clk, which in this case is the one coming from the Peripheral PLL (CLK_32KHz). The external clock source in this register refers to the one from the 32K oscillator (CLK_32K_RTC), which is connected to an external 32KHz crystal.
The 32KHz Oscillator (which generates CLK_32K_RTC) is the same thing as OSC1. So the enable bit in OSC_REG enables/disables this oscillator. The linux function you reference writes a 0x48 to the OSC_REG, which sets bit6 and clears bit5 (basically enabling the clock to the RTC) and sets bit3 (selects external clock source, from the 32KHz crystal)
The TRM excerpt that you mention confuses the terms 'internal' and 'external' and also references rcosc_ctrl incorrectly. Basically it is calling the CLK_32K_RTC as an internal source (since the oscillator connected to the crystal is actually in the RTC module), and the external source is the one coming from the Peripheral PLL (since that PLL is external to the RTC module). This is enabled using OSC_REG, not rcosc_ctrl.
The rcosc_ctrl register controls the 32KHz RC oscillator. This is the oscillator which derives 32KHz from the master oscillator using an RC network, and produces CLK_RC32K which can be used by for timers or GPIO debouncing. As mentioned before, this cannot be used for the RTC.
We will get the information fixed in the DM and TRM in future releases.
James, thanks so much for your really helpful clarifications. Just two minor questions about.
In our custom board we have a 32 KHz crystal: if I set the OSC_REG to use the CLK_32KHz (from PLL), the crystal circuit will be started to oscillate in any case? This source is used also for purposes other than RTC (such as DTIMER1_1ms and CLKOUT2 signal), so I wonder if it will run in any case even when RTC is not using it as source.
In TRM Section 184.108.40.206.12: "DMTIMER1 is implemented using the DMTimer_1ms module which is capable of generating an accurate 1ms tick using a 32.768 KHz clock. During low power modes, the Master Oscillator is disabled. CLK_32KHZ also would not be available in this scenario since it is sourced from the Master Osc based PER PLL. Hence, in low power modes DMTIMER1 in the WKUP domain can use the 32K RC oscillator for generating the OS (operating system) 1ms tick generation and timer based wakeup."Is it an error of the TRM, or is the 32K RC Oscillator really not available when the Master Oscillator is disabled (as derived from it)? Or am I missing something?
Thanks one again. Best regards,
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