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As mentioned in your other E2E forum post titled “Ethernet PHY connection and configuration“, the KSZ9021 has different default timing for the RGMII signals. 

You must configure the KSZ9021 to meet the timing requirements defined in the AM335x data sheet.

The receive data is transferred with respect to the receive clock and the transmit data is transferred with respect to the transmit clock. You need to insure all timing parameters of both devices are within the specified operating range.  This may require timing adjustments via the KSZ9021RL RGMII Clock and Control Pad Skew and RGMII RX Data Pad Skew registers.

Note: The AM335x has the internal delay mode enabled by default and this is not supported so you must disable the internal delay mode in AM335x and adjust RGMII timing using the timing adjustment features in KSZ9021.

Regards,
Paul

Hi,

I had disable the internal delay by changing file in "ti-sdk-am335x-evm-05.03.00.00/board-support/u-boot-2011.09-psp04.06.00.02/board/ti/am335x/evm.c"  

int board_init(void)
{
 __raw_writel(0x00111010, gmii_sel); --------------------disable internal delay, enable RGMII

In adjustment of RGMII timing of KSZ9021 micrel phy, i have no idea how to do it. Any tutorial that i can refer ?

Thanks & Regards

Keldy

To change the phy timings you use the MDIO interface to modify phy registers. In u-boot, you would use the miiphy_read() and mmiphy_write() routines. In u-boot, look in evm.c for the evm_phy_init() routine. You can see where code reads registers MII_PHYSID1 and MII_PHYSID2 to determine which phy is used. You would want to add code to test for your phy and, if found, program the RGMII Clock and Control Pad Skew register (address 260) and the RTMII RX Data Pad Skew register (address 261). I found these addresses in the Micrel datasheet.

I asked Paul for more information about these registers and he said:

He needs to check the timing of each RGMII signal.  This calculation is done by using the minimum setup/hold time input requirements, the min/max output characteristics, and PCB propagation delays of each signal to determine how to configure these registers. 

For example, the RX data to RX clock output characteristics of the KSZ9021 is +/-500ps and the AM335x input requires a minimum 1ns setup and hold time to operate properly.  If the PCB propagation time of RX data and RX clock are equal, the RX clock would need to be delayed in the KSZ9021 about 1.5ns - 2ns to center the clock edge in the valid data window.

Steve K.

Hi,

Thanks for reply.

I know nothing about RGMII calculation and RGMII signal tunning. I'll try study some RGMII document to learn.

Please continue to support me in this issue.

Thanks & Regards

Keldy

Hi,

base on ksz9021 datasheet, the TskewT min/max is +/- 500ps, TskewR max is 2.6ns, AM335x setup/hold time min is 1ns, assume PCB propagation delay is same.

RXC skew delay about 1.5ns(500ps + 1ns) to 3.1ns(500ps + 2.6ns) 

TXC skew delay about 1.5ns(500ps + 1ns) to 3.1ns(500ps + 2.6ns)

RXCTL, TXCTL, RXD[0-3] skew delay set to 0ns

ksz9021 phy, register 260: 

register 261

 Am i correct with the register new configuration? 

Thanks & Regards

Keldy

Hi,

How about the RXD[0-3] skew delay ? leave it to default value 0x7777, or change to 0x0000 ?

The miiphy_read() and miiphy_write() function only allow 8 bits phy register address, writing value to phy register 0x104 and 0x105 using miiphy_write() make writing value to phy register 0x04 and 0x05.

Any other method to write to phy register 0x104 and 0x105?

Thanks & Regards

Keldy

Keldy, please post back here if you have success getting the Micrel PHY to work with these settings.  We are laying out a board with the same PHY and may have to go through the same process.  Perhaps if we can get the Micrel chip timings right we can add support for this phy to the u-boot tree.

It looks like there shouldn't be anything changed in the kernel right?  Just in u-boot?

Hi,

Yes, just in uboot.

Thanks & Regards

Keldy

Hi Keldy,

Any luck with the PHY? I have absolutely the same problem. I've stumbled upon this thread and am just curious if you get it work. I've tried everything including Extended Registers with no luck. And Micrel's tech support is just unresponsive, to say the least.

Thank you,

Vlad.

Hi,

My custom PCB board just arrived, before this i just jump wire to test the micrel PHY. but i facing the UART0 boot problem now, will come back to this after i fix the boot problem.

Thanks & Regards

Keldy

Hi,

it works! it was the skew delay problem. The ethernet driver is generic.

setting the micrel phy register (0x104) to value 0x9797, and register(0x105) to value 0x0000 make my ethernet working. But there is a failure sometime, need to tune the skew delay properly to make sure working properly.

Many Thanks to Paul, Steve K, and DK.

Thanks & Regards

Keldy 

Hi Keldy,

You mentioned above that you were only making changes in U-boot, not Linux. In U-Boot, is it operating at 100Mbit/s or 1000Mbit/s? Did you get it to work in Linux?

Currently we have the same PHY operating at 100Mbit/s, and only in U-boot. Our skew delays are slightly different (more optimized for the required delay and our hardware setup), and we're setting them in both U-boot and Linux, but in U-boot it is limited to 100Mbit/s and in Linux it comes up and then goes down as soon as it is actually configured with the cpsw driver. Therefore, I'm curious if you actually got it to work in Linux.

Thanks,
Russell 

Hi,

only make changes in u-boot, i use ' mii ' command to write data to phy register, operating speed is 100Mbit/s, and i can boot kernel image and file system through network, and i can telnet into my board from linux PC. For 1000Mbit/s i haven't test yet. At least know AM335x SDK driver can support micrel phy, what need to do is tuning the skew.  

Thanks and Regards

Keldy