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TI Home » TI E2E Community » Support Forums » ARM® Processors » Sitara™ ARM® » AM3x Sitara ARM Processors Forum » How to configure the priority between the Ethernet ports
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How to configure the priority between the Ethernet ports

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Daisuke Maeda
Posted by Daisuke Maeda
on May 07 2012 19:15 PM
Genius3040 points
How is the priority between two CPGMAC_SL Ethernet ports configured?

Best regards,

Daisuke
 
AM335x CPSW Ethernet Subsystem CPSW_3G
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  • -DK-
    Posted by -DK-
    on May 08 2012 09:30 AM
    Expert6790 points

    Daisuke,

    Are you wanting to configure the Ethernet Class of Service (CoS) priority levels or the physical port priority levels?

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  • Daisuke Maeda
    Posted by Daisuke Maeda
    on May 08 2012 19:54 PM
    Genius3040 points

    Hi -DK-,

    Thank you for your reply.

    I am wanting to configure the internal port priority levels.

    I saw the CPSW_3G Block Diagram(Figure 14-6) in the TRM(SPRUH73E) and found out that each CPGMAC_SL has a single GMII interface.
    Therefore, I thought that the internal port priority levels depended on CPGMAC_SL.

    Best regards,

    Daisuke

     

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  • peaves
    Posted by peaves
    on May 09 2012 00:02 AM
    Genius12795 points

    I would like to clarify something related to the AM335x  Gigabit Media Independent Interface (GMII) signals.

    Each CPGMAC_SL natively contains a GMII port which can be internally multiplexed a GMII to RMII gasket, GMII to RGMII gasket, or to a subset of AM335x MII pins.  Only the GMII signals required to implement MII were multiplexed directly to pins.  This allows each  CPGMAC_SL to be connected to a 10/100 Mbps RMII PHY via the GMII to RMII gasket, a 10/100/1000 Mbps RGMII PHY via the GMII to RGMII gasket, or a 10/100 Mbps MII PHY via the subset of AM335x MII pins.

    We retained the GMII signal names for the pins since this matched the internal signal names which are also references in the CPSW documentation.  However, the upper four bits on each data path and the source-synchronous transmit clock signals were not connected to pins to reduce the number of pins.  This limits the GMII signals to MII operation.

    This may cause someone to think they can connect a GMII PHY.  Therefore, I wanted to clarify this before someone spends time trying to connect a GMII PHY.

    Regards,
    Paul

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  • -DK-
    Posted by -DK-
    on May 09 2012 16:10 PM
    Verified Answer
    Verified by Daisuke Maeda
    Expert6790 points

    Daisuke,

    There is no way to set internal port priority levels, however, depending on your application you may find that traffic shaping via the Rate Limit Mode discussed in section 14.3.2.10.3 of the TRM (SPRUH73E) could serve your purpose by limiting one port to a lower ingress/egress rate than the other. Again, this would depend on the nature of your application and traffic.

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  • Daisuke Maeda
    Posted by Daisuke Maeda
    on May 10 2012 23:49 PM
    Genius3040 points

    Hi -DK-,

    Thank you for your reply.

    Are there the configurations (except the Rate Limit Mode) which affect the internal traffic?

    Best regards,

    Daisuke

     

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  • -DK-
    Posted by -DK-
    on May 11 2012 13:06 PM
    Verified Answer
    Verified by Daisuke Maeda
    Expert6790 points

    Daisuke,

    The switch also supports QoS (Quality of Service) via the Priority Code Point bits of the 802.1Q header in the Ethernet frame which could be used to shape traffic internally; there are no other methods to control port priority from a hardware standpoint.

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  • Daisuke Maeda
    Posted by Daisuke Maeda
    on May 13 2012 19:13 PM
    Genius3040 points

    Hi -DK-,

    Thank you for your help.

    Best regards,

    Daisuke

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