Hello,I am using Pin Mux Utility v2.4.1.0 for AM335x.Although I would like to use GPMC_DIR with GPMC_CSN2, GPMC_CSN4, its setting indicates IO Set Violation on Pin Mux Utility.I have searched about restriction of pin combination on datasheet and TRM, but I can not find.
Could you let me know... - Where is the detail of restriction of pins combination?
- Can you disclose what combinations are restricted? Best regards,RY
Hi Ry,
This may help you : http://processors.wiki.ti.com/index.php/Pin_Mux_Utility_for_ARM_MPU_Processors_v2#IO_Set_Violation_Status
I think that GPMC_DIR is the problem. You probably can use it only in a specific configuration of GPMC where CSN2 or CSN4 could not be used or where GPMC_BE1N_MUX1 and GPMC_WAIT0 should be used (there is not violation with that modes).
Best Regars
Cyril
I had the same issue and eliminated the problem by not driving the GPMC_WPN to the NAND Flash and also by swapping GPMC_CS2 by GPMC_CS3.
Regards,
Elvis