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Update: 

The Upper word always reads back the same value. For my original test, I was writting 0x0000, but I switched it to 0xDEAD and it reads back 0xDEAD in every upper word as well as every 4th address will read back as "0xDEADDEAD".

I have verified that the DDR CK signals are running at 166 MHz. 

I modified the timing registers and am having some success. 

Here is my test: 

for ( k = 0; k < RAM_LENGTH; k++ )
 {
    pRam[k] = k + ((k+1) << 16);
 }

for ( k = 0; k < RAM_LENGTH; k++ )
 {
    if ( pRam[k] != (k + ((k+1) << 16)) )
       err[i]++;
 }

Failures are about 25% of the time, or every 4th 32-bit address. 

If I use a Memory Browser in CCS set to address 0x8000_0000, with continuous refresh enabled, Some values are changed. These are predominately in at every fourth 32-bit address (offsets of 0x0C, 0x1C, 0x2C, 0x3c...).

Additionally, the value at address 0x8000_0000 is being returned as 0xFFFF_FFFF.

It looks like you still have a timing issue.  Double check both the DDR PHY Register settings (use the Ratio Seed Spreadsheet to obtain the proper values for your board) and the AC timing register settings (use the AM335x DDR Calculation too for the proper values for your board)

If you think you have all of those correct and are still seeing errors, try adjusting CMDx_PHY_CTRL_SLAVE_RATIO higher:  0x100 or 0x200.

Regards,

James

Increasing CMDx_PHY_CTRL_SLAVE_RATIO make the issue worse. 

Using the Ratio Seed spreadsheet, I get these values:

I am using Starerware as a base, so I followed the same code as in the AM335x bootloader DDR configuration:

HWREG(DATA0_RD_DQS_SLAVE_RATIO_0) = ((0x40 << 30)|(0x40 << 20)|(0x40 << 10)|(0x40 << 0));
HWREG(DATA0_RD_DQS_SLAVE_RATIO_1) = (0x40 >> 2);

I've adjusted the PHY timings to reduce my errors, but I still have errors. For my simple test above, I get occasional failures ( < 1%). However, if I read the memory location again, the expected value is returned.

Here are my DATA phy seed values:

#define BSP_EMIF_RD_DQS_SEED (0x12)
#define BSP_EMIF_WR_DQS_SEED (0x01)
#define BSP_EMIF_PHY_WRLVL_SEED (0x00)
#define BSP_EMIF_PHY_GATELVL_SEED (0x00)
#define BSP_EMIF_PHY_FIFO_WE_SEED (0x80)
#define BSP_EMIF_PHY_WR_DATA_SEED (0x40)
#define BSP_EMIF_PHY_LOCK_DIFF (0x00)
#define BSP_EMIF_PHY_RANK0_DELAY (0x01)

more work to continue tomorrow....

Jay, you shouldn't need to touch any other PHY registers other than the ones explained in the wiki.  Here is an example from an EVM with LPDDR:

#define  CMD_PHY_CTRL_SLAVE_RATIO        0x80
#define  CMD_PHY_INVERT_CLKOUT           0x0

#define  DATA_PHY_RD_DQS_SLAVE_RATIO     0x40
#define  DATA_PHY_FIFO_WE_SLAVE_RATIO    0x52  //RD_DQS_GATE
#define  DATA_PHY_WR_DQS_SLAVE_RATIO     0x0
#define  DATA_PHY_WR_DATA_SLAVE_RATIO    0x40  //WRITE_DATA

#define  DDR_IOCTRL_VALUE                (0x18B)

Your values may be different, but these are the only ones that need to be modified. 

Then, you also need to adjust the AC timing registers in the EMIF controller. based on the memory datasheet values.

Regards,

James

Hello JayWhy, JJD,

I've also been trying to set up my mDDR registers, and I have a question..

1. The Ratio seed only provided 4 values of the 5 that was mentioned in the chain...the 1 value that it didn't provide is the CMDx_PHY_CTRL_SLAVE_RATIO. This value is seem to be set to 0x80 for mDDR - is that a standard value or does it need to be calculated.

Thanks a lot for your replies.

Regards

Santhosh