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16MBytes of NOR flash on the GPMC interface and both PRU MII interfaces
I need some help understanding how TI configured the pin mux to interface NOR flash to AM3359 on the AM335X_15X15_ICE.dsn development board.The reference design shows a 2 Mbyte flash driven with address lines a[0:15] tied to flash pins a[0:15], and lines a[20:23] tied to flash pins a[16:19].From the pin_mux_utility it appears lines a[20:23] carry signals a[20:23]. Is the flash address space discontinuous or signals lines a[20:23] carry signals a[16:19]?What we need is at least 16MBytes of NOR flash on the GPMC interface and both PRU MII interfaces. The desire is to use one FLASH device and no glue glue logic but the best I can come up with is a latch and 2 FLASH devices.
1) Does this force discontinuous memory access?
2) What is the maximum NOR flash supported and accesible with both PRU MII's used?
Please refer to the errata on ICE board: http://www.ti.com/litv/pdf/spruhf6
You are right. The NOR Flash has limitation in how many addresses can be accessed when PRU subsystem's MII pins are also to be used. It will result in non-contiguous addressing from the perspective of AM335x.
The addresses will be available such that 16 address lines (multiplexed with data) are available on GPMC to connect to a external device. Then, GPMC_A[6...] are available. Connecting these will mean the software has to take care of non-contiguous addressing.
The errata states that the correct pinout configuration uses GPMC_A[6:9], but the board shows GPMC_A[20:23]. Also in reviewing a specific case the _A[6:9] correspond to the MII1_RXD[0:2] & MII1_MR1_CLK, where as the GPMC_A[20:19] are free and look to be correct.
Is the pin_mux file available for the EVM (or the .h file)?
The GPMC_A[20:19] are not correct. Please refer to latest version of Technical Reference Manual and consult table 7.5.
The pin-mux file is something we are working on.
I'm probably just dense, but I'm trying to figure out the GPMC layout on the ICE. From table 7.5 in the TRM, it seems to indicate that for a 16-bit multiplexed device, the next address line to use after the multiplexed version of GPMC_AD would be GPMC_A (or perhaps GPMC_A as applied to the M29W160EB on the ICE, as it starts at A0). But the ICE erratta regarding these pins states "...for higher bits on the address bus, the expected signals to be connected from the AM335X device are the GPMC_A[4:1]..."
I'm not following how non-multiplexed A4..A1 would be the expected signals to connect to A19..A16 on the NOR flash, and table 7.5 in the TRM also seems to support this by showing GPMC_A4..A1 as "Not Used" in the "multiplexed address data 16-bit device" scenario.
OK, so what am I missing?
Please download the latest technical reference manual. It has correction in Table 7-5.
Uggh....I can't believe I fell for the old "don't bother checking for updated documentation".
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