• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 102 subscribers
  • Views 2230 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Design Considerations for AM335x DDR3

Kika
Intellectual 420 points 
Hello,

We have few AM335x DDR3 Questions from our 3P.
We understood that the Datasheet's "DDR3 Routing Guidelines" should 
be strictly followed, but we wonder if the below kind of usage leads to a problem.

AM3352 High-Speed Bypass Capacitors:
- Datasheet Table 5-56 mentions VDDS_DDR HS bypass capacitor count as "20"
 isn't this number a little bit more. There are only 7 VDDS_DDR pins.
 so we have only one capacitor on each pin. Will this be a problem?

Longest Manhattan distance for the data bus:
- In the Datasheet DQLMn is defined as DQ Longest Manhattan distance.
 Is it possible to let us know the reason behind choosing DQLMx as Longest Manhattan distance.
 In our case instead of DQLMx = 37mm, in order to maintain Length matching with all the address
 signal group, DQLMx will be 45mm. Will this be a problem?

Trace spacing:
- "Center-to-center DQ[x] to other DDR3 trace spacing" is mentioned as 4W
but in our case that could be <4W(2W)
and also DQ[x] to other DQ[x] trace spacing is mentioned as 3W
but in our case that could be <3W(2W).
Will this lead to a problem?

Regards.
  • 0
    TI__Guru 55375 points

    All of the recommendations in the DDR3 guidelines are based on a system level simulation used to verify DDR3 operation with AM335x.  It may be possible to implement a functional DDR3 design without following all of the requirements described in the routing guidelines, but TI recommends designers verify their non-compliant design with a system level simulation.

    You are not the first person to question the number of bypass capacitors shown in the DDR3 routing guidelines.  It may be possible to reduce the number of capacitors, but you should perform a system level simulation of your design to verify DDR3 operation.

    The trace spacing described in the DDR3 routing guidelines were based on minimizing crosstalk from adjacent signals.  It may be possible to reduce the trace spacing, but you should perform a system level simulation of your design to verify DDR3 operation.

    Regards,
    Paul

  • 0 in reply to peaves
    TI__Guru 55375 points

    I forgot to answer your question about DQLMn in my first reply.

    DQLMx is the sum of DQLMXx and DQLMYx; where x = the byte number, X = the distance of the X axis, and Y = the distance of the Y axis.  This is shown in the figure titled “DQLM for Any Number of Allowed DDR3 Devices”.  This parameter only applies to the respective data byte signals.

    DQLM0 is the longest Manhattan distance for the DQS0 and DQ0 net class signals defined in the “Clock Net Class Definitions” and “Signal Net Class Definitions” tables.

    DQLM1 is the longest Manhattan distance for the DQS1 and DQ1 net class signals defined in the “Clock Net Class Definitions” and “Signal Net Class Definitions” tables.

    For example, DQLM0 describes the worst case longest distance of the DQS0 and DQ0 net class signals.  So you should be able to begin your PCB design by applying a length match requirement in the PCB layout tool to all data byte 0 signals that is equal to DQLM0.

    CACLM is the equivalent parameter for the clock and address signals.  This parameter does not need to be length matched with the DQLM0 or DQLM1 parameters.

    Regards,
    Paul

  • 0 in reply to peaves
    Intellectual 420 points

    Hello Peaves,

    Thank you so much for the detailed answer.

    We will definitely do the system level simulation.

    Regards. 

  • 0 in reply to peaves
    Expert 2115 points
    Hello Peaves,
    so while routing the DDR3 Data lines , DQLM , which is the longest Manhattan length should be the maximum etch length of lines.
    What if the Etch length is more than the Max Manhattan and we do the length matching to the longest trace. Will it be an issue.
    Ie suppose my DQ5 is having the max Manhattan of about 790mils , and my DQ1 is having Manhattan of about 690 and etch length of 990 mils, what should i do ? Length match DQ1 and all others to DQ5 or Length match DQ5 and others to Dq1.

    Regards,
    Eby Jayan