Regarding AM3352 NAND Flash Interface

This question is not answered

Posted by Siddharth Chowdhuri

on Apr 17 2012 10:54 AM

Prodigy10 points

Hi,

Listed below are few queries regarding the NAND Flash interface with AM3352.

With AM3352, the bootstrap pins is configured for booting from NAND Flash at CS0. The max size of this NAND flash at CS0 can be 64Gb. Please confirm if my understanding is correct.
The bootstrap pins configured for booting from NAND Flash in AM3352. After PoR, the registers GPMC_CONFIG default value will be set for accessing the NAND Flash at CS0 for ex - GPMC_CONFIG1_i registers as mentioned in Table 7-11, Section 7.1.3.3.12.1.1 will be set for accessing the NAND Flash. Also the NAND Device Command, Address Phase Control will be automatically taken care. Please confirm if my understanding is correct.

Regards,

Siddharth

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