Starterware pin-muxing on Beaglebone - AM3x Sitara ARM Processors Forum - Sitara™ ARM®

I'm left confused setting the pin mux of the Beaglebone and hoping some for help here.

I want to access the McASP0 pins on the P8 connector and have tried a few things without much success. According to the Beaglebone user manual (section 7.13) the McASP pins I need access to reside on:

mcasp0_ax1 -> pin31 (name: "uart5_ctsn")

mcasp0_fsr -> pin33 (name: "uart4_rtsn")

mcasp0_aclkr -> pin35 (name:uart4_ctsn")

mcasp0_axr0 -> pin36 (name: "uart3_ctsn")

To configure the pin mux using the Starterware code I use the following piece of code:

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_CTSN(5)) = CONTROL_CONF_MUXMODE(3); // mcasp0.axr -> transmit : pin=31

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_RTSN(4)) = CONTROL_CONF_RXACTIVE | CONTROL_CONF_MUXMODE(3); // mcasp0.fsr -> transmit : pin=33

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_CTSN(4)) = CONTROL_CONF_RXACTIVE | CONTROL_CONF_MUXMODE(3); // mcasp0.aclkr -> transmit : pin=35

HWREG(SOC_CONTROL_REGS + CONTROL_CONF_UART_CTSN(3)) = CONTROL_CONF_RXACTIVE | CONTROL_CONF_MUXMODE(3); // mcasp0.axr0 -> receive : pin=36

where

#define CONTROL_CONF_UART_CTSN(n) (0x968 + ((n) * 0x10))
#define CONTROL_CONF_UART_RTSN(n) (0x96c + ((n) * 0x10))

Since my project doesn't work I wonder one of you can at least verify that the pin muxing is correct?

Best Regards

Tom

Hello Tom

I had the same problems.

I used the "names" of MODE0 and now it is working.I didn't change any of the defines.

My code looks like this:

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(8)) = CONTROL_CONF_MCASP0_ACLKX_CONF_MCASP0_ACLKX_RXACTIVE | MCASP_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(9)) = CONTROL_CONF_MCASP0_FSX_CONF_MCASP0_FSX_RXACTIVE | MCASP_SEL_MODE;

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(12)) = CONTROL_CONF_MCASP0_ACLKR_CONF_MCASP0_ACLKR_RXACTIVE| MCASP_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(13)) = CONTROL_CONF_MCASP0_FSR_CONF_MCASP0_FSR_RXACTIVE | MCASP_SEL_MODE;

    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(10)) = CONTROL_CONF_MCASP0_AXR0_CONF_MCASP0_AXR0_RXACTIVE | MCASP_SEL_MODE;
    HWREG(SOC_CONTROL_REGS + CONTROL_CONF_LCD_DATA(14)) = CONTROL_CONF_MCASP0_AXR1_CONF_MCASP0_AXR1_RXACTIVE | MCASP_SEL_MODE;

If you know how to send with an external clock you can tell men ;-)

best regards

Basti