Hello Champs,
Do we have Verilog model available for DDR controller - that can be shared?
We need Verilog model. Verilog model is used to carry our Signal Integrity and Timing Analysis using SI tool such as HyperLynx from Mentor Graphics.
Is there any othjer tool set you recommend?
Thanks & Best Regards
Feroz
You can use the IBIS models for the DDR inteface simulation to check for Signal Integrity. IBIS models are available from the product folder www.ti.com/am3358. Please review the Section 5.4.2 in the data manual. If you follow these guidelines, you don't require any timing simulations.
Regards, Siva