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Sitara Processors Forum
Redundant Master along with TI Slave Implementation
I'm trying to prototype a EtherCAT Redundant Network using a SOEM master on Linux and TI ICE AM 3359 dev kits.
Using the TI code, I can get a daisy chain working from Master-Ethernet Port0 but when I try the daisy chain from the other port (Master-Ethernet Port1), the whole system being connected together as a ring, I don't get any answer.
Is there a direction constraint on the slave code?
Is that something that can be configured within the ESI file?
Would you be able to give some guidance to achieve this?
this is a documented limitation of the current EtherCAT slave implementation on AM335x. We do not support redundancy mode yet. So slaves can't be addressed through the OUT port. Unfortunately it is caused by a silicon bug that is documented in silicon errata. A new chip rev is in the works to fix this.
Only with the new silicon we will be available to implement redundancy mode support. Sorry for that.
can you confirm which silicon errata this is in?
Is this limited to the ICE boards, or also the IDK as well?
Please see here: http://www.ti.com/lit/er/sprz360a/sprz360a.pdf
In this document, Advisory 1.0.4 mentions the low level hardware circuitry issue. It has to do with switching the clock from one MII port to another when the MII ports are being switched to recover from media failure in redundant mode. You might be able to see that the fix itself is going to be very simple but its implication on EtherCAT is that we have to delay support of redundant links. The PRU firmware itself has it enabled already (and verified on development platforms) but we cannot show it on AM335x devices until few more months.
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