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How to use DDR of AM335x
How to use the reg_phy_rd_local_odt Field in the DDR_PHY_CTRL_1 Register.
What is the Full thevenin load (01b)? In the case of Full thevenin load (01b), is ODT impedance 75ohm, or 150ohm?
What is the Half thevenin load (11b)? In the case of Half thevenin load (11b), is ODT impedance 50ohm, or 75ohm?
AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (Rev. F)http://www.ti.com/lit/ug/spruh73f/spruh73f.pdf22.214.171.124 DDR_PHY_CTRL_1 Register (offset = E4h) [reset = 0h]
How to use the ddr_wuclk_disable Field in the ddr_io_ctrl Register.
What is the WUCLKIN?
What is the ISOCLKIN?
What is the SLOW (32k) clock? When clock is synchronously gated, what does the clock synchronize with?
AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (Rev. F)http://www.ti.com/lit/ug/spruh73f/spruh73f.pdf9.3.52 ddr_io_ctrl Register (offset = E04h) [reset = 0h]
How to use the vref_ctrl Register.
What is the BIAS2?
What is the VDDS/2? Is the VDDS/2 the DDR_VREF?
AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (Rev. F)http://www.ti.com/lit/ug/spruh73f/spruh73f.pdf9.3.54 vref_ctrl Register (offset = E14h) [reset = 0h]
How to do the Address Mapping
When REG_IBANK_POS=0 and REG_EBANK_POS=0,
What is the maximum number of banks interleaved within a device (per chip select)? Is it all the banks?
Is the interleaving of banks between the two chip selects possible?
The current AM335x is only one chip select (DDR_CSn)! For the current AM335x which setting in the Address Mapping is available?
AM335x ARM Cortex-A8 Microprocessors (MPUs) Technical Reference Manual (Rev. F)http://www.ti.com/lit/ug/spruh73f/spruh73f.pdf126.96.36.199 Address Mapping188.8.131.52.1 Address Mapping when REG_IBANK_POS=0 and REG_EBANK_POS=0
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