Questions regarding AM3358
Hello, I am currently considering using the ARM processor, AM3358 and have a few questions about it as stated below
1. About the DPLL Power Supply Requirement
The table above indicates that “Max peak-to-peak supply noise” of “VDDS_PLL_DDR” is 0 mV.
I would like to make sure that this information is correct. Could you confirm whether or not “Max peak-to-peak supply noise” of “VDDS_PLL_DDR” is 0 mV ?
2. About Designing the Input Clock
1) I am considering connecting both OSC0 and OSC1 to LVCMOS Digital Clock Source. In that case, is it okay if I set the Input Clock Voltage Level to 1.8[V] which is the same voltage level for VDDS_OSC?
2) As for the GNDs shown in the figure below, is it okay if I set them as Normal Digital Grounds?
Your prompt response regarding this request would be greatly appreciated.
If you have any questions regarding this request, please contact me through email.
I look forward to hearing from you soon. Thank you for your help in advance.
Sang Gil. Shin.
Thanks for highlighting the AM335x Data Sheet error. The Max peak-to-peak supply noise of VDDS_PLL_DDR should be 50 mV.
The LVCMOS digital clock source connected to the OSC0 XTALIN terminal should be powered by the same source as connected to VDDS_OSC terminal.
The LVCMOS digital clock source connected to the OSC1 RTC_XTALIN terminal should be powered by the same source as connected to VDDS_RTC terminal.
Both VDDS_OSC and VDDS_RTC terminals have a recommended nominal operating voltage of 1.8 volts.
The OSC0 VSS_OSC terminal and OSC1 VSS_RTC terminal should be connected to the digital ground when using external LVCMOS clock sources.
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