Hi all
There is a timing structure in am335xevm SDK:
struct gpmc_timings { /* Minimum clock period for synchronous mode (in picoseconds) */ u32 sync_clk; /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */ u16 cs_on; /* Assertion time */ u16 cs_rd_off; /* Read deassertion time */ u16 cs_wr_off; /* Write deassertion time */ /* ADV signal timings corresponding to GPMC_CONFIG3 */ u16 adv_on; /* Assertion time */ u16 adv_rd_off; /* Read deassertion time */ u16 adv_wr_off; /* Write deassertion time */ /* WE signals timings corresponding to GPMC_CONFIG4 */ u16 we_on; /* WE assertion time */ u16 we_off; /* WE deassertion time */ /* OE signals timings corresponding to GPMC_CONFIG4 */ u16 oe_on; /* OE assertion time */ u16 oe_off; /* OE deassertion time */ /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */ u16 page_burst_access; /* Multiple access word delay */ u16 access; /* Start-cycle to first data valid delay */ u16 rd_cycle; /* Total read cycle time */ u16 wr_cycle; /* Total write cycle time */ /* The following are only on OMAP3430 */ u16 wr_access; /* WRACCESSTIME */ u16 wr_data_mux_bus; /* WRDATAONADMUXBUS */};
I'm not sure about some items:
1:
u16 access; /* Start-cycle to first data valid delay */
Where is the "start-cycle"? Where is the start of the other signal timing, e.g. cs_on? Does it start from "start-cycle" too?
2:
u16 rd_cycle; /* Total read cycle time */
What's this "Total read cycle time"? I think it maybe start from "start-cycle" mentioned above (Am I correct?). But where is its finish point?
For convenience I paste a timing diagram here, we can talk according this diagram.
Thank you very much.
could any body help me?
Hi,
I found that we_on and oe_on can not set. no matter how big a value you set when initialize, it will be set to adv_on time if you observe via an oscilloscope.
I think adv_on should at the same time address valid. So I don't know how to get the timing descripted by the diagram above.
If I set adv_on earlier than the cs_on to get address timing, then oe_on and we_on will earlier than cs_on. This is not valid, especialy for read.
if I set adv_on later than the cs_on to get a right timing for oe_on and we_on, then the address will later than the cs.
How should I set the timing structure to achieve the diagram above?
Lihua
Note: If this answer solves your question please mark post as "Answered"
Hi Biser,
Thank you for your reply. I've solved that problem. Reason: I copied the retiming function from nand_retiming function. in that function, set oe_on = adv_on. and we_on = oe_on, So I can't set my oe_on and we_on.
Thank you.