Is the CS size supported max 128Mbytes on AM335x GPMC?

Sorry, let me correct a little.

RY9983 said:

On TRM(spruh73g: P255), there is the description that GPMC have A0-A26 address on 16bit access.
It means that max 128Mbyte address is supported.

I think GPMC CS size is max 128MByte on AM335x.
Is it correct?

On TRM(spruh73g: P255), there is the description that GPMC have A0-A26 address on 16bit access.
It means that max 256Mbyte address is supported.

But, since A26 does not drive signal, I think that the GPMC CS size is max 128MByte(A0-A25) on AM335x.
Is it correct?

Best regards,
RY

Hello, Biser.

Thank you for your reply.
About A1-A27 is ok.
On TRM, one description is A26-A0 and the other is A27-A1.
Therefore, your advice is consistent with my understanding.

Can I have an additional question?

Actually, I am using GPMC as multiplexed address/data 16-bit mode.
So, GPMC_AD[15:0] and GPMC_A[11:1] are used to drive address.
But, when I set GPMC_CONFIG7->MASKADDRESS = 0(CS size = 256Mbyte), I have seen data abort.

Is GPMC_CONFIG7->MASKADDRESS = 0 supported?

Best regards,
RY

Hello, Biser.

I am sorry, the data abort was my mistake.
Now, I have been able to set GPMC_CONFIG7->MASKADDRESS = 0(256MByte) without data abort.
But, the GPMC_A[11] have not been driven.
Other address pins GPMC_A[10:1] can operate completely.

I would like to attach the sample.
Could you check this?
5516.gpmc.zip

Describes about detail:  
- I am using TMDXEVM3358.  
- GPMC and Pinmux are set by original.gel.  
- The gpmc.out is simple write access for GPMC.  
- You can see the GPMC_A[x] on J6 connector of TMDXEVM3358 base board.

Best regards,
RY

Hello, Biser.

Thank you for your kindness. I will be waiting for help of yours.

> have you checked the pinmux setting of A11?

Yes, I have. I am using V17 of ZCZ package as GPMC_A11. And, I am setting conf_gpmc_a11 = 0. Also other GPMC_A[10:1] are similar settings. conf_gpmc_aXX = 0

Best regards, RY

Hello, Biser and TI supporting team.

Sorry to trouble you.
Was there any progress has been?
I am waiting for information of yours.

Best regards,
RY

Hello, Biser.

Thank you very much for your information.
I understood that the GPMC supports 256MByte per CS on AM335x.
I would like to check my sample source again.

Best regards,
RY

Hello, Biser.

Thank you very much for helping me.
I checked my gpmc sample.
But, GPMC_A[11] have not been driven yet.

My checking is:

 - CM_PER_GPMC_CLKCTRL = 0x2; // GPMC ICLK Enable

 - GPMC_CONFIG1_0 = 0x00001200; // Address/Data Multipexed, 16bit, Async Mode
 - GPMC_CONFIG7_0 = 0x00000050; // 256MB CS0 enabled, Base Addres=0x10000000

 - CONTROL_CONF_GPMC_AD0 = 0x20; // rx_enabled, mode0
 - ...
 - CONTROL_CONF_GPMC_AD15 = 0x20; // rx_enabled, mode0

 - CONTROL_CONF_GPMC_A1 = 0x0; // mode0
 - ...
 - CONTROL_CONF_GPMC_A11 = 0x0; // mode0

 - SYSBOOT[11:10] = 10b .. XIP boot muxed device
 - SYSBOOT[8] = 1b .. 16bit device

GPMC_A1-A10 can be completely driven.
But, only GPMC_A11 can not be driven.

Is my check enough?
Where should I need to check the other?

Best regards,
RY

Hello, Biser.

Thank you for your help.
Although I changed the GPMC_A11 to Mode 4, I can not see the signal on GPMC_A11 pin.
I am checking J6[28] pin on AM3358EVM.

I would like to send you my register dumping.

// Pad conf regs.
0x44E10840 = 0x00000000 // conf_gpmc_a0
... all 0 ...
0x44E10868 = 0x00000000 // conf_gpmc_a10
0x44E1086C = 0x00000004 // conf_gpmc_a11 is mode4

// GPMC regs.
0x50000050 = 0x00000A00 // GPMC_CONFIG is set as no limited address
0x50000060 = 0x00001200 // GPMC_CONFIG1_0 is set as 16bit, A/D mux mode
0x50000078 = 0x00000040 // GPMC_CONFIG7_0 is set as CS enabled, 256MB, Base Address = 0x0

And my program is below:

volatile unsigned int *p = (volatile unsigned int *)0x0F000000;
*p++ = 0xFFFFFFFF;

On GPMC_A10-A8, I can see the signals. J6[27:25]
But, I can not see only GPMC_A11. J6[28]

Is my checking correct?

Best regards,
RY

Hello, Biser.
OK. I am waiting for your reply.
Best regards, RY

Hello RY, 

That is strange.  I have the same setup.  Using an EVM and checking J6[28] while triggering on J4[25](CS0).  Can you check to make sure you have control of j6[28] by setting 0x44e1086c to 0x17?  that should make the line go high by setting it to GPIO and enabling the pull up.  I just want to make sure there isn't something else driving that pin for some reason on your board. 

Hello, Jeff.

Thank you so much for your advise.
I understand. I would like to recheck it on other EVM(SK, IDK).
I am out of office this week. I will get back to you after confirming.
Thanks for helping.

Best regards, RY

Hello, Jeff-san,

Sorry for my late reply.
I checked it on my TMDXEVM3358 and TMDXIDK3359.

Although I could not see the driving of GPMC_A11 pin(J6[28]) on both targets,(I can see the operation as gpio.)
I heard that it can be driven on EVM from TI local FAE.
We are confirming the difference of these now.

I will send you feedback again.
Best regards, RY

Hi RY,

Now, I have been able to set GPMC_CONFIG7->MASKADDRESS = 0(256MByte) without data abort.
But, the GPMC_A[11] have not been driven.
Other address pins GPMC_A[10:1] can operate completely.

Have you solved your problem that you are not able drive the A11 signal ?

If you got fixed, could you please update us, so that it could help others.

Titusrathinaraj-san,

From my memory, I could not find the root cause, but GPMC_A[11] have been driven completely in our customer's target.
So, any troubles did not occur.
And, also GPMC_A[11] can be seen in the EVM of TI Local FAE support.

Best regards, RY

Hi RY,

Sounds good.

Thanks for your update.

I'm glad that you were able to fix it.

From my memory, I could not find the root cause, but GPMC_A[11] have been driven completely in our customer's target.
So, any troubles did not occur.
And, also GPMC_A[11] can be seen in the EVM of TI Local FAE support.

Could you please elaborate what you have done to fix the problem.

We have a customer who is facing the same problem as yours.

Is there any configuration issue or any thing else ?

I think, we have to configure the "gpmc_a11"  pin as MODE4 ie "gpmc_a27" for 256MB muxed device, Right ?

Are you able to drive "gpmc_a27"  (using MODE4)?

How did you configure the "gpmc_a11" pad  ie MODE0 or MODE4 ?

Whether the NOR flash device is muxed or non-muxed ?

If it is a muxed device, Have you followed 4th column of "Table 7-5. GPMC Pin Multiplexing Options"  in AM335x TRM ?

We are desperately in need of help. Please do reply.